background image

– 31 –

– 32 –

• IC Block Diagrams
– RF Board –

IC11

CXA1992BR

FZC

VC

TDFCT

TZC

ATSC

TEI

LPFI

TEO

VEE

EI

E

F

FE

BIAS

SL P

SL M

SL O

ISET

VCC

XRST
DATA

XLT
CLK

LOCK

SENS2

SENS1
C. OUT

VCC

DFCTO

IFB1 – IFB6

BAL1 – BAL4

TOG1 – TOG4

FS1 – FS4

TG1 – TG2

TM1 – TM7

PS1 – PS4

TGH

TGL

BALH

BALL

ATSC

DFCT

TM1

TG1

FS2

IFB1 – IFB6

VCC

VEE

VCC

VEE

VEE

PD 2

I-V AMP

FOK

CC2

CC1

CB

CP

RF O

RF I

RFTC

PD2

PD1

PD

LD

RF M

TA

 O

TA

 M

FSET

TG2

TGU

SRCH

FEO

FEI

FDFCT

FGD

FLB

FE O

FE M

TZC

FZC

FOL

FOH

MIRR

LDON

LPCL

LPC

TGFL

DFCT1

CC1

1

2

3

4

5

6

7

8

9

10

26

25

24

23

22
21

20

19

18

17

16

15

14

40

41

42

43

44

45

46

47

48

49

50

51

52

39

PD 1

I-V AMP

38

PD

AMP

37

LD

AMP

LASER

POWER

CONTROL

FOCUS BIAS

WINDOW

COMPARATOR

FOCUS ERROR

AMP

F I-V
AMP

E I-V
AMP

TGFL

TRACKING GAIN

WINDOW

COMPARATOR

E-F BALANCE

WINDOW

COMPARATOR

ATSC

WINDOW

COMPARATOR

TZC

COMPARATOR

TRACKING PHASE

COMPENSATION

CENTER

VOLTAGE

GENERATOR

FZC

COMPARATOR

FOCUS PHASE

COMPENSATION

CHARGE UP

FSET

ISET

IIC DATA REGISTER, INPUT SHIFT REGISTER,

ADDRESS DECODER, SENSE SELECTOR,

OUTPUT DECODER

TTL

IIL

IIL

TTL

IIL

TTL

RF SUMMING

AMP

FOCUS OK

COMPARATOR

PEAK/BOTTOM

HOLD

PEAK/BOTTOM

HOLD

DEFECT

AMP

MIRR

COMPARATOR

36

34

31 30

29

28

27

35

33 32

BAL1 – BAL4

TM6

TM2

VCC

VEE

TM5

11

12

13

TG2

TM4

VCC

VEE

TM3

FS1

VCC

VEE

TOG1 – TOG4

TM7

FS4

DFCT

+

+

IC52

BA6287F

1

2

3

4

OUT1

VM

VCC

FIN

8

7

6

5

GND

OUT2

VREF

RIN

CONTROL LOGIC

TSD

POWER

SAVE

DRIVER

DRIVER

– MAIN Board –

IC101

CXD2530Q

1 2 3 4 5 6

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

43
42

41
40

39
38

37

36

35

34

33

32
31

50
49

48
47

46

45

44

88
89

90
91

92
93

94

95

96

97

98

99

100

81
82

83
84

85

86

87

71 70 69 68

67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

80 79 78 77 76 75 74 73 72

ASYMMETRY

CORRECTOR

DIGITAL

PLL

CLOCK

GENERATOR

D / A

INTERFACE

DIGITAL CLV

SUB CODE

PROCESSOR

TIMING

LOGIC

CPU

INTERFACE

SERVO

AUTO

SEQUENCER

ERROR

CORRECTOR

16K RAM

DIGITAL OUT

OSC

EFM

DEMODULATOR

TES6

VDD

VSS

EXCK

SBSO

SCOR

WFCK

TES5

EMPH

DOUT

C4M

FSTT

XTSL

MNT0

MNT1

MNT3

XROF

C2PO

RFCK

GFS

XPCK

XUGF

GTOP

VDD

VSS

TES4

BCK

TES3

PCMD

TES9

LRCK

WDCK

ASYE

ASYO
ASYI

BIAS

RF

AVDD

CLTV

AVSS

FILI

FILO
PCO

VCTL

V16M

VCKI

VPCO1

VPCO2

TES1

TES0

LOCK

PWMI

MDP

MDS

VSS

MON

FOK

VDD

SPOD

XLON

SPOB

SPOC

CLKO

SPOA

DATO

XLTO

SEIN

CNIN

XLAT

CLOK

SENS

DATA

SQCK

SQSO

TES2

CKOUT

LMUT

RMUT

VDD

VSS

NC

XRST

VSS

NC

NC

VDD

NC

TES8

XVSS

VSS

XTAI

XTAO

VSS

XVDD

TES7

NC

VDD

NC

NC

VSS

Содержание CDX-600 - Compact Disc Changer System

Страница 1: ...NGER US Model CDX 600 606 Canadian Model AEP Model UK Model CDX 600 E Model CDX 626 SPECIFICATIONS CDX 600 606 626 Model Name Using Similar Mechanism CDX 505RF CD Drive Mechanism Type MG 250C 137 Optical Pick up Name KSS 521A J2N Photo CDX 600 ...

Страница 2: ...r IC Block Diagrams The components identified by mark or dotted line with mark are critical for safety Replace only with part number specified Les composants identifiés par une marque sont critiques pour la sécurité Ne les remplacer que par une piéce portant le numéro spécifié 21 22 Page 27 ...

Страница 3: ...CDX 600 606 626 27 28 7 6 SCHEMATIC DIAGRAM MAIN Section 1 2 See page 18 for Waveforms See page 33 for IC Block Diagrams Page 22 ...

Страница 4: ...CDX 600 606 626 29 30 7 7 SCHEMATIC DIAGRAM MAIN Section 2 2 See page 18 for Waveforms See page 33 for IC Block Diagrams ...

Страница 5: ...EAK BOTTOM HOLD PEAK BOTTOM HOLD DEFECT AMP MIRR COMPARATOR 36 34 31 30 29 28 27 35 33 32 BAL1 BAL4 TM6 TM2 VCC VEE TM5 11 12 13 TG2 TM4 VCC VEE TM3 FS1 VCC VEE TOG1 TOG4 TM7 FS4 DFCT IC52 BA6287F 1 2 3 4 OUT1 VM VCC FIN 8 7 6 5 GND OUT2 VREF RIN CONTROL LOGIC TSD POWER SAVE DRIVER DRIVER MAIN Board IC101 CXD2530Q 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 43 ...

Страница 6: ...RIN CONTROL LOGIC TSD POWER SAVE DRIVER DRIVER DIGITAL FILTER CIRCUIT ATTENUATOR OPERATIONAL CIRCUIT DEEMPHASIS FILTER CIRCUIT D MODULATION CIRCUIT INTERFACE CIRCUIT TEST CIRCUIT OUTPUT CIRCUIT ANALOG FILTER TIMING GENERATOR OSC MICROCOMPUTER INTERFACE CIRCUIT OUTPUT CIRCUIT ANALOG FILTER 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 21 22 23 24 LRCK BCK DATA HS SM ATT EMP SH BS LA VDX XO XI ...

Страница 7: ...r on 15 to 23 O Not used open 24 AUTO ON OFF I Setting terminal for the automatic adjustment L automatic adjustment H manual adjustment fixed at L in this set 25 to 29 O Not used open 30 RESET I System reset signal input from the reset signal generator IC202 and SONY bus interface IC204 L reset For several hundreds msec after the power supply rises L is input then it changes to H 31 EXTAL I Main s...

Страница 8: ... I Initialize signal input for the EEPROM H format Fixed at L in this set 67 O Not used open 68 SINGLE I Setting terminal for the single disc multiple discs mode L single mode H multiple discs mode fixed at H 69 FOK I Focus OK signal input from the CXA1992BR IC11 L NG H OK 70 GFS I Guard frame sync signal input from the CXD2530Q IC101 L NG H OK 71 SENS1 I Internal status signal sense signal input ...

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