K800 - K810
1202-3085 rev. 2
APPENDIX
A
P
P
E
NDIX
N2000 ASIC Vincenne 2 A07 1.8V Cu-Plug Thin Ni (Pb Free Package)
ROP1013066/6
N2200 LDO 1.3V RYT1137810/1
Pin Configuration Diagram
SUB
SIM
OFF
ONSW
A
ONSW
B
ONSW
C
VDD_F
VBAT_
F
VDD_ G
LED2
SIM
VCC
VDD
_IO
SIM
CLK
SDA
V
BUCK
VDD
BUF
MCLK
AUXI3P
MIC1P
AUXI1P
VDD_D
VBAT_
B
LDOd,e
SCL
VSS_D
CHRG
LED1
VSS
BEAR
AUXI2N
MIC1N
AUXI2P
DAC
STR
PWR
RST
AUXI3N
BEARN
PCMO
PCM
SYN
IREF
VDD
LP
VDD_IO
_18
SIM
DAT
MOD_
USB
BEARP
PCM
CLK
SDAT
VDD
BEAR
SCLK
SRST
VSS
CODEC
DCIO
VDD
CODEC
AUXO1
CH
REG
DAC
CLK
LINE P
VIBR
DACO2/
4
CCO
SLEEP
DACO3
AUXI1N
SIM
RST
EXT
LDO
VREF
XTAL1
B
DATA
AD
STR
IRQ
TEST
GPA13
GPA12
AUXO2
CLK_
REQ
GPA6
Vbat-D
CHRG,
SIM
VBAT_
A
LDOa,b
VDD_A
VDD_B
DAC
DAT
VDD
ADC
CHSEN
SE+
CHSEN
SE-
VSS
PA
VBUS
VSS_B
SIM
VSS_A
ANA-
LOG
VSS
ADC
LINE N
PCMI
PASEN
SE+
FGSEN
SE-
FGSEN
SE+
PASEN
SE-
FF_IN
IOUT
PA
REG
EXP
OUT
GPA1
GPA2
GPA4
GPA3
VDD_E
GPA5
GPA7
VSS
BUCK
BOOST
ISENSE
+
DACO1
VDD
BUCK
SW
BUCK
SW
BOOST
BOOST
ISENSE
-
VBAT_
C
VSS_C
BUCK
DCDC
VDD
PA/
DAC
DEC0
A
B
C
D
E
F
G
H
J
K
L
M
1
2
3
4
5
6
7
8
9
10
11
12
VSS
TH 1
VSS
TH 3
VSS
TH 2
VSS
TH 15
DEC4
VSS
TH 14
VSS
TH 21
VSS
TH 9
VSS
TH 22
VSS
TH 30
VSS
TH 8
VSS
TH 12
VSS
TH 11
DEC3
VSS
TH 13
VSS
TH 10
DIG
VSS
VSS
TH 5
VSS
TH 6
V
BOOST
VSS
TH 4
VSS
TH 7
MOD1
VSS
TH 17
VSS
TH 18
BOOST
FB+
VSS
TH 19
VSS
TH 26
VSS
TH 25
VSS
TH 27
DIG
VDD
View of Pin Configuration Diagram (as seen from top of package)
Package Information
SYMBOL
COMMON DIMENSIONS
2.10
1.90
0.80
MAX.
0.70
MIN.
0.20 REF.
0.40
0.05
2.10
0.20
0.00
1.90
D
A
L
A1
E
A2
k
0.25 MIN.
TOP VIEW
TDFN
2mm x 2mm
R
N.C.
I.C.
OUT
N.C.
IN
SHDN
1
2
3
ESET
4
8
7
6
GND
5
Pin Configurations
Pin Description
8-PIN
TDFN
(2mm x 2mm)
NAME
FUNCTION
8
IN
Regulator Input. Supply voltage can range from +1.62V to +3.6V. Bypass IN
with at least a 1μF ceramic capacitor to GND (see the
Capacitor Selection and
Regulator Stability
section).
—
GND
Ground. GND also functions as a heatsink. Solder to a large pad or circuit-
board ground plane to maximize SOT23 power dissipation.
5
GND
Ground
6
SHDN
Active-Low Shutdown Input. A logic-low reduces supply current to below 1μA.
Connect to IN or logic-high for normal operation.
4
RESET
Open-Drain, Active-Low Reset Output.
RESET
rises
100ms after the output has achieved regulation.
RESET
falls
immediately if V
OUT
drops below 82.5% of its nominal voltage, or if the
device
is
shut down.
.C.
I
nternally Connected. Leave floating or connect to GND.
1
OUT
Regulator Output. Sources up to 300mA. Bypass with a 4.7μF low-ESR
ceramic capacitor to GND.
2, 7
N.C.
No Connection. Not internally connected.
—
EP
Ground. EP also functions as a heatsink. Solder EP to a large pad or circuit-
board ground plane to maximize TDFN power dissipation.
3
Components N2000 - N2200
SEMC Electrical Repair Manual
94
(121)
Содержание K800
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