SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 103
Version 1.7
9.5.5 USB ENDPOINT 3 ENABLE REGISTER
The communication with the USB host using endpoint 3, endpoint 3’s FIFO is implemented as 8 bytes of dedicated
RAM. The endponit3 is an interrupt endpoint.
0A4H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
UE3R UE3E FFS3 UE3DO UE3DI UE3C3 UE3C UE3C1 UE3C0
Read/Write R/W
R
R/W
R/W R/W R/W R/W R/W
After
reset
0 0 0 0 0 0 0 0
Bit [3:0] UE3C [3:0]:
Indicate the number of data bytes in a transaction: For IN transactions, firmware loads the
count with the number of bytes to be transmitted to the host from the endpoint 3 FIFO.
Bit 4
UE3DI:
Indicate endpoint 3 data ready to host (IN token).
0 = Data is ready in EP6 FIFO for USB host drawing out. Firmware set the bit zero to indicate that data is
ready. Hardware will send an ACK to complete the transaction and set the bit to 1 after the IN token
transaction.
1 = Data is not ready in EP6 FIFO for IN token. Hardware will send NAK handshakes response to any IN
token sent to this endpoint. In addition, set this bit and the bit 6 of UPID register will send the STALL
handshake response to any IN token sent to this endpoint.
Bit 5
UE3DO:
Indicate endpoint 3 data ready from host (OUT token).
0 = Data doesn’t finish carrying. Data doesn’t finish carrying. Clear the bit by firmware after the FIFO data is
already read.
1 = Data carries successfully, and data is ready in EP3 FIFO.
.
Bit 6
FFS3
: endpoint 3 FIFO selection control bit.
FFS3
UE3DO=1, endpoint OUT data
UE3DI=1, endpoint IN data
0
FIFO 1
FIFO 0
1
FIFO 0
FIFO 1
Bit 7
UE3E:
USB endpoint 3 function enable bit.
0 = disable USB endpoint 3 function.
1 = enable USB endpoint 3 function.
9.5.6 USB DATA POINTER 0 REGISTER
FIFO 0’s address pointer. Use the point to set the FIFO address for reading data from FIFO and writing data to FIFO.
0A5H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
UDP0
UDP04 UDP03 UDP02 UDP01 UDP00
Read/Write
-
-
- R/W R/W R/W R/W R/W
After
reset
- - - 0 0 0 0 0
Address [07]~address [00]: data buffer for endpoint 0. Check the bit 7 of the USTATUS register (0xA9H) to select the
right FIFO.
Address [0F]~address [08]: data buffer for endpoint 1. Check the bit 6 of the UE1E register (0xA2H) to select the right
FIFO.
Address [17]~address [10]: data buffer for endpoint 2. Check the bit 6 of the UE2E register (0xA3H) to select the right
FIFO.
Address [1F]~address [18]: data buffer for endpoint 3. Check the bit 6 of the UE3E register (0xA4H) to select the right
FIFO.
The following examples show how to do select the right FIFO address pointer.
