75ERV
60
* AGP Master 1 ws
write
Leave this field at default.
* AGP Master 1 ws
read
Leave this field at default.
CPU & PCI Bus Control
* PCI1 Master 0 WS
Write
When Enabled, writes to the PCI bus are executed
with zero wait states.
The choice: Enabled, Disabled.
PCI1 Master 0 WS Writer
PCI2 Master 0 WS Write
PCI1 Post Write
PCI2 Post Write
PCI Delay Transaction
Item Help
Menu Level
CMOS Setup Utility - Copyright (C) 1984-2001 Award Software
CPU & PCI Bus Control
:Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
Enabled
Enabled
Enabled
Enabled
Disabled
* PCI2 Master 0 WS
Write
Leave this field at default.
* PCI Delay Transac-
tion
Leave this field at default.
* PCI2 Post Write
Leave this field at default.
* PCI1 Post Write
Leave this field at default.
Содержание SL-75ERV
Страница 1: ...R T h e S o u l O f C o m p u t e r T e c h n o l o g y Mainboard SL 75ERV User Manual V1 1...
Страница 14: ...14 75ERV MEMO MEMO...
Страница 34: ...34 75ERV MEMO MEMO...
Страница 42: ...75ERV 42 MEMO MEMO...
Страница 47: ...Chapter 4 BIOS Setup 47 Award Flash Memory Writer Start Screen Award Flash Memory Writer Complete Screen...
Страница 83: ...Chapter 4 BIOS Setup 83 MEMO MEMO...
Страница 94: ...APPENDIX 94 MEMO MEMO...