3. Built-In Options
The Si823Hx EVB comes from the factory configured to provide VOA, GNDA, VOB and GNDB signals out to the connector J5.
This allows the evaluation of the Si823Hx drivers on their own. However, the board provides pads in which the customer can place
components to build a half bridge for the Si823Hx to drive. This allows the customer to evaluate the Si823Hx driver in a manner that is
closer to a real application.
To configure the board for a half bridge circuit, the following components must be removed:
• R3
• R9
• R11
Also, components for the following reference designators must be added:
• R7
• U3 or U4
• U5 or U6
The positions for U3, U4 provide an option for the customer to place a FET that is either a TO-220 package or a D-PAK package for
the high side of the half-bridge. These two components are wired in parallel. They should not both be populated at the same time. The
same is true for U5 and U6 for the low side device. The customer is free to place virtually any component in those positions to evaluate
the Si823Hx driver in a circuit that resembles their intended application.
In addition to these options, there is a footprint for D4 and D5 as well as R4 and R8. This allows the customer to optimize the turn
on and turn off currents for the FET’s if they choose to do so. It should be noted that these diodes do not exist on the Si823H9-EVB.
The Si823H9 driver provides separate pull-up and pull-down outputs making it unnecessary to use a diode. The resistors used for this
purpose on the Si823H9-EVB are R4, R5, R8 and R10.
Furthermore, resistors R6 and R13 are footprints provided for the customer to add pull down resistors to turn off each FET should
something prevent the VOA/VOB outputs from pulling the gate circuits low.
If these options are implemented, the pinout of J5 changes slightly. Pin 1 remains connected to GNDB and would be used for the
half-bridge supply ground. Pin 2 becomes the output of the half-bridge. Pin 3 is no longer connected to anything. Pin 4 becomes the
half-bridge positive supply.
Another option on the evaluation board is the setting of JP2. If a shunt is connected between pins 2 and 3 of JP2, the VDDA pin
of the Si823Hx is connected to J2. This allows the customer to evaluate the Si823Hx driver with independent supplies. If a shunt
is connected between pins 1 and 2 of JP2, then the VDDA pin is connected to diode D3 which is then connected to VDDB. This
creates a boot strap supply for the A driver. In this configuration, capacitor C3 becomes the boot strap capacitor. It may be necessary
to modify the value of C3 to optimize the performance of the boot strap supply. Please see our boot strap calculation tool online at
https://www.skyworksinc.com/tools/Pages/bootstrap-calculator.aspx
Note:
The Si823H9 and Si82520 evaluation boards are populated with dual drivers that have a high side/low side (HS/LS) operation.
This means that if both VIA and VIB inputs are driven high, the device’s overlap protection will force both VOA and VOB to a low state.
However, the Si823H9-EVB is built with two single channel drivers. This means there is no overlap protection. If the customer populates
the half-bridge components, they must make sure that both inputs are never driven high at the same time. Doing so will cause both FET
devices to turn on at the same time and short circuit the bridge supply. This will almost certainly damage the FET devices and likely
damage the Si823H9 devices as well.
UG367: Si823Hx/8252x-EVB User's Guide • Built-In Options
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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Rev. 0.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 23, 2022
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