SITRONICS LCD-1502, Руководство по обслуживанию

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Information of ICs
IC201 (MX88L284)
Pin No Port Name Function Pin No Port Name Function
1 BUSTYPE Bus type select 111 OSDB OSD BLUE input
2
VDDP PAD Power
112 OSDBLNK OSD select.
3-10 PIXINA [7:0]
Pixel input A GREEN [7:0} from ADC. Y[7:0]: Color data from Video
Decoder
113 VDD Core Power
11 CLAMP Clamp signal 114 DQM2 Data mask byte enable (For SGRAM)
12-19 PIXINA [15:8]
Pixel input A GREEN [7:0} from ADC. CbCr[7:0]: Color data from
Video Decoder.
115 DQM3 Data mask byte enable (For SGRAM)
20
VDD Core Power
116
GNDP PAD GND
Pix input A BLUE[7:0] from ADC.
117-124 MD[31:24]
Memory data input/output
D23: MPLLC2, (Video input clk signal)/2.
125
VDDP PAD Power
D22: MPHS, Video input Hsync signal.
126-133 MD[23:0]
Memory data input/output
D21: MPVS, Video input Vsync signal.
134
GNDP PAD GND
D20: MPODD, Video input Odd/Even field signal.
135
MCLK Memory clock
D19: MPHREF, Video input horizontal reference signal.
136
GND Core GND
D18: MPLLC, Video input clk signal.
137
MA10 Memory address
D17: MPCREF, Video input clk reference signal.
138
VDDP PAD Power
D16: MPVREF, Video input vertical reference signal.
139-148 MA[9:0]
Memory address
29
DDE Digital display enable input pin
149
GNDP PAD GND
30
GND Core GND
150
CKE Memory clock enable
31
GNDP PAD GND
151
WE# Write Enable
32,33
AGND Analog GND
152
CAS# Column address strobe
34
X1 Analog pad for Reference Frequency Input for ternal
153
RAS# Row address strobe
35
XO Analog pad for rReference Frequency Output for internal oscillator.
154
VDDP PAD Power
36,37
AGND Analog GND
155-156 DQM[0:1]
Data mask byte enable (For SGRAM)
38
VDDP PAD Power
157
GNDP PAD GND
39-45
BB[7:0} BLUE DATA (Even)
158
GND Core GND
46
GNDP PAD GND
159-166 MD[15:8]
Memory data input/output
47
BB0 BLUE DATA (Even)
167
VDDP PAD Power
48
VDDP PAD Power
168
VDD Core Power
49-56
GB[7:0] GREEN DATA (Even)
169
MD7 Memory data input/output
57
GNDP PAD GND
170
GNDP PAD GND
58-64
RB[7:0] RED DATA (Even)
171-177 MD[6:0]
Memory data input/output
65 VDDP PAD Power 178-185 AD[7:0]
Multiplexed low_order address and data bus
66
RB0 RED DATA (Even)
186
GNDP PAD GND
67 GNDP PAD GND 187 CPUA15/BCS
high_order a15 address input, or BIU Valid cycle.
(for ISA bus debug)
68
LCKB Even data clock output for LCD display
188
VDDP PAD Power
69
GND Core GND
189
ALE Address Latch Enable for 8051 Bus.
70
LCKA Odd data clock output for LCD display
190
WR# Memory Read Strobe
71
GNDP PAD GND
191
RD# Memory Read Strobe.
72-79
BA[7:0] BLUE DATA (Odd)
192
TMCLK External MCLK input
80-87
GA[7:0] GREEN DATA (Odd)
193
RSTZ# System reset.
88
VDD Core Power General I/O
89
VDDP PAD Power GPIO[0]: Hsync source select
90
RA 7 RED DATA (Odd) GPIOA[1]: ADC-Coast source select
91
GNDP PAD GND GPIO[3]: DS for External ADC
92-98
RA[6:0] RED DATA (Odd)
GPIO [4] PDEN for External PLL
99
LHSYNC HSYNC output for LCD display GPIO [5] Input select
100
LVSYNC VSYNC output for LCD display 200 IRQ Interrupt request
101
LDTG Data Enable output for LCD display 201 SOGCS Input Sync on Green composite Sync
102 OSDB0/GOUT1
Extended OSD RED input or use as Motorola OSD intensity input
(Output Share With GOUT4)
202 TDCLK/CSYNC External DCLK input/Composite Sync input
103
GNDP PAD GND 203 HSYNC1 Input HSYNC
104 GOUT1 General Output1
204 VSYNC1 Input VSYNC
105 VDDP PAD Power
205 GOUT3 General Output 3
107 12CDATA 12C DATA Pull up by internal 168K Ohm resistor 206 GND Core GND
108 12CCLK 12C CLK. Pull up by internal 168K Ohm resistor 207 DCLKA Input dot clock
109
OSDR OSD RED input 208 GNDP PAD GND
110
OSDG OSD GREEN input
GPIOA[0:5]
PIXINA[23:16] 21-28
194-199
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