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7.9.7 Interrupt Handling
The interrupt flags are sampled and captured at each machine cycle. All interrupts are sampled at the rising edge of the clock.
If one of the flags was set, the CPU will find it and the interrupt system will generate a LCALL to the appropriate service
routine, LCALL generated by hardware is not blocked by any of the following conditions:
An interrupt of equal or higher priority is already in progress.
The current cycle is not in the final cycle of the instruction in progress. In other words, any interrupt request cannot get
response before executing instructions to complete.
The instruction in progress is RETI or visit the special register IEN0/1 or IPLH instruction. This ensures that if the instruction in
progress is RETI or read and write IEN0/1 or IPLH then at least one more instruction except RETI will be executed before any
interrupt is vectored to; this delay guarantees that the CPU can observe the changes of the interrupt status.
Note:
Since priority change normally needs 2 instructions, it is recommended to disable corresponding Interrupt Enable flag to avoid
interrupt between these 2 instructions during the change of priority.
If the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. Every polling
cycle interrogates only the valid interrupt requests.
The polling cycle/LCALL sequence is illustrated below:
Interrupt
Latched
Interrupt
Polled
Long Call to
Interrupt Vector Service
Interrupt
service
Cn+8
C2
C1
Interrupt
Pending
C3
Interrupt
Signal
Generated
C3~Cn
Cn~Cn+7
Interrupt Response Time
The hardware-generated LCALL pushes the contents of the program counter onto the stack (but it does not save the PSW).
Then vector address of the corresponding interrupt source (referring to the interrupt vector table) will be stored in the program
counter.
Interrupt service execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs
the processor that the interrupt routine is no longer in progress, and then pops the top two bytes from the stack and reloads
the program counter. Execution of the interrupted program continues from the point where it was stopped. The RET instruction
can also return to the original address to continue, but the interrupt priority control system still think the interrupt in a same
priority is responsed, in this case, the same priority or lower priority interrupt will not be responsed.
7.9.8 Interrupt Response Time
If an interrupt is detected, its request flag will be set in every machine cycle after detection. The value will be kept by the
internal circuitry until the next machine cycle; the CPU will generate an interrupt at the third machine cycle. If the request is
active and conditions are right for it to be acknowledged, hardware instruction LCALL will call service routine which requeste
interrupt at the next instruction to be executed. Otherwise the interrupt will pending. The call itself takes 7 machine cycles.
Therefore, from the external interrupt request to start the implementation of interrupt program requires at least 3+7 completed
machine cycle.
A longer response time would be obtained if the request was blocked by one of the above three previously listed conditions. If
an interrupt of equal or higher priority is already in progress, the additional wait time obviously depends on the length of the
other interrupt’s service routine.
If the instruction in progress is not in its final cycle and the instruction in progress is RETI, the additional wait time is 8 machine
cycles. For a single interrupt system, if the next instruction is 20 machine cycles long (the longest instructions DIV & MUL are
20 machine cycles long for 16 bit operation), adding the LCALL instruction 7 machine cycles the total response time is
2+8+20+7 machine cycles.
Thus interrupt response time is always more than 10 machine cycles and less than 37 machine cycles.
