Block diagram
A9 A8 BDIR BC2 BC1 DA7~DA0
o o o o o |
| | | | | |
| | | | | |
| | --- Bus Control ---o Bidirectional -----o I/O Port A <=> IOA7~IOA0
| | | Decoder o--- buffer |
| | | o |
| | | | |
| | o o |
Register Addr --o Address --o Register o-------|
Latch Decoder Array -----o I/O Port B <=> IOB7~IOB0
o
|
--------------------------------------
| | | | |
o o | o o
Noise Music | Envelope Level Frequency
Generator Generator | Generator --o Control o----- divider ---o CLOCK
| | | | master |
| o | | clock |
-------o Mixer o-- | ---------o SEL
| |
| |
o |
D/A Convertor o------------------
| | |
| | |
Analog Channel
o o o
A B C
Description of pins
1. DA7 ~ DA0
This is an 8 bit bidirectional data bus which is used for moving data and
addresses between the SSG and CPU. In the read and write modes, DA7 ~ DA0
corresponds to B7 ~ B0 of the register array. In the address mode, DA3 ~ DA0
is used for the register address, and DA7 ~ DA4 is used together with A9 and
A8 for the upper address.
2. A8 and A9
These are the upper address input pins. A8 has pullup resistance while A9
has pulldown resistance. When the voltage level at A8 while the level at A9
and DA7 ~ DA4 is low, the address mode is selected allowing for the fetching
of a register address. Connect A8 and A9 to +5V and ground respectively when
not in use.
3. RESET
Reset is effective when the voltage level is low, and the contents of all
registers in the array are reset to '0'. This pin has pullup resistance.
4. CLOCK
Supplies the master clock to the sound generator and envelope generator. This
is equipped with a 1/2 frequency divider which allows for the use of a
frequency which is 1/2 of the input clock, as the master clock.
5. SEL
When SEL is driven to the high level, the input clock is taken as the master
clock. When the voltage level of SEL is low, the input clock is divided by 2
to obtain the master clock. This pin has pullup resistance, allowing for
full pin compatibility with the AY-3-8910 manufactured by AI, when this pin
is not connected to anything.
Version: v005
19
Date: 22.05.2012
