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Silicon Laboratories SI4734-B20, Руководство по эксплуатации продукта

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Silicon Laboratories SI4734-B20 Скачать руководство пользователя страница 17

S i 4 7 3 4 / 3 5 - B 2 0

Rev. 1.0

17

2.  Typical Application Schematic

Notes:

1.

Place C1 close to V

DD

 pin.

2. 

All grounds connect directly to GND plane on PCB.

3. 

Pins 1 and 20 are no connects, leave floating.

4. 

To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal 
Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 

5. 

Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.

6. 

RFGND should be locally isolated from GND.

7. 

Place Si4734/35 as close as possible to antenna jack and keep the FMI and AMI traces as short as possible.

8. 

See “AN382: Si4734/35 Designer’s Guide” for further recommendations.

20

19

18

17

16

U1

Si4734/35-GM

NC
FMI
RFGND

AMI
RST

DOUT

LOUT

ROUT

GND

VDD

NC

GPO1

GPO2

GPO3

DFS

SE

N

SC

LK

SD

IO

RC

LK

VIO

SEN

SCLK

SDIO

1
2
3

4
5

15

14
13
12
11

6

7

8

9

10

RST

RCLK

C1

VBATTERY
2.7 to 5.5 V

VIO

1.5 to 3.6 V

FMI

C2

C3

X1

RCLK

GPO3

Optional: for crystal oscillator option

C5

L1

L2

LOUT
ROUT

GPO1
GPO2/INT

DCLK

DFS

DOUT

Optional: Digital Audio Output

R1

R2

R3

C4

Содержание SI4734-B20

Страница 1: ...nd 3 wire control interface 2 7 to 5 5 V supply voltage Wide range of ferrite loop sticks and air loop antennas supported 3 x 3 x 0 55 mm 20 pin QFN package z Pb free RoHS compliant Table and portable...

Страница 2: ...Si4734 35 B20 2 Rev 1 0...

Страница 3: ...eo DAC 23 4 11 Soft Mute 23 4 12 RDS RBDS Processor Si4735 Only 23 4 13 Tuning 24 4 14 Seek 24 4 15 Reference Clock 24 4 16 Control Interface 24 4 17 GPO Outputs 26 4 18 Firmware Upgrades 26 4 19 Rese...

Страница 4: ...ply Voltage VDD 0 5 to 5 8 V Interface Supply Voltage VIO 0 5 to 3 9 V Input Current3 IIN 10 mA Input Voltage3 VIN 0 3 to VIO 0 3 V Operating Temperature TOP 40 to 95 C Storage Temperature TSTG 55 to...

Страница 5: ...rrent IIO 320 600 A VDD Powerdown Current IDDPD 10 20 A VIO Powerdown Current IIOPD SCLK RCLK inactive 1 10 A High Level Input Voltage3 VIH 0 7 x VIO VIO 0 3 V Low Level Input Voltage3 VIL 0 3 0 3 x V...

Страница 6: ...h does not occur within 300 ns before the rising edge of RST 2 When selecting 2 wire mode the user must ensure that SCLK is high during the rising edge of RST and stays high until after the first star...

Страница 7: ...0 ns SCLK SDIO Capacitive Loading Cb 50 pF Input Filter Pulse Suppression tSP 50 ns Notes 1 When VIO 0 V SCLK and SDIO are low impedance 2 When selecting 2 wire mode the user must ensure that a 2 wire...

Страница 8: ...arameters Figure 3 2 Wire Control Interface Read and Write Timing Diagram SCLK 70 30 SDIO 70 30 START START STOP tf IN tr IN tLOW tHIGH tHD STA tSU STA tSU STO tSP tBUF tSU DAT tr IN tHD DAT tf IN tf...

Страница 9: ...s SDIO Input to SCLK Hold tHSDIO 10 ns SEN Input to SCLK Hold tHSEN 10 ns SCLK to SDIO Output Valid tCDV Read 2 25 ns SCLK to SDIO Output High Z tCDZ Read 2 25 ns SCLK SEN SDIO Rise Fall time tR tF 10...

Страница 10: ...Input to SCLK Hold tHSDIO 10 ns SEN Input to SCLK Hold tHSEN 5 ns SCLK to SDIO Output Valid tCDV Read 2 25 ns SCLK to SDIO Output High Z tCDZ Read 2 25 ns SCLK SEN SDIO Rise Fall time tR tF 10 ns Note...

Страница 11: ...20 to 85 C Parameter Symbol Test Condition Min Typ Max Unit DCLK Cycle Time tDCT 26 1000 ns DCLK Pulse Width High tDCH 10 ns DCLK Pulse Width Low tDCL 10 ns DFS Set up Time to DCLK Rising Edge tSU DFS...

Страница 12: ...reo Separation7 9 25 dB Audio Mono S N3 4 5 7 10 55 63 dB Audio Stereo S N4 5 7 10 11 58 dB Audio THD3 7 9 0 1 0 5 De emphasis Time Constant6 FM_DEEMPHASIS 2 70 75 80 s FM_DEEMPHASIS 1 45 50 54 s Audi...

Страница 13: ...maximum for all tests Tested at RF 98 1 MHz 2 To ensure proper operation and receiver performance follow the guidelines in AN383 Antenna Selection and Universal Layout Guidelines Silicon Laboratories...

Страница 14: ...emphasis Time Constant FM_DEEMPHASIS 2 70 75 80 s FM_DEEMPHASIS 1 45 50 54 s Audio Common Mode Voltage9 0 7 0 8 0 9 V Audio Output Load Resistance5 9 RL Single ended 10 k Audio Output Load Capacitance...

Страница 15: ...0 1 0 5 Antenna Inductance Long Wave LW 2800 H Medium Wave AM 180 450 Powerup Time From powerdown 110 ms Notes 1 To ensure proper operation and receiver performance follow the guidelines in AN383 Ant...

Страница 16: ...768 40000 0 kHz RCLK Frequency Tolerance 50 50 ppm REFCLK_PRESCALE 1 4095 REFCLK 31 130 32 768 34 406 kHz Crystal Oscillator Crystal Oscillator Frequency 32 768 kHz Crystal Frequency Tolerance 100 100...

Страница 17: ...ace and pin 4 connects to the AM antenna interface 6 RFGND should be locally isolated from GND 7 Place Si4734 35 as close as possible to antenna jack and keep the FMI and AMI traces as short as possib...

Страница 18: ...oupling capacitor 0 47 F 20 Z5U X7R Murata L1 Ferrite loop stick 180 450 H Jiaxin L2 4 7 H Coilcraft U1 Si4734 35 AM FM Radio Tuner Silicon Laboratories Optional Components C2 C3 Crystal load capacito...

Страница 19: ...d seek algorithms soft mute auto calibrated digital tuning and FM stereo processing In addition the Si4734 35 provides analog or digital audio output and a programmable reference clock The device supp...

Страница 20: ...w IF architecture with a minimum number of external components and no manual alignment required This digital low IF architecture allows for high precision filtering offering excellent selectivity and...

Страница 21: ...when the DFS is low In DSP mode the DFS becomes a pulse with a width of 1 DCLK period The left channel is transferred first followed right away by the right channel When transferring the digital audi...

Страница 22: ...INVERTED DCLK OFALL 1 OFALL 0 I2 S OMODE 0000 LEFT CHANNEL RIGHT CHANNEL 1 3 2 n n 1 n 2 1 3 2 n n 1 n 2 LSB MSB LSB MSB DCLK DOUT DFS INVERTED DCLK OFALL 1 OFALL 0 Left Justified OMODE 0110 1 3 2 n...

Страница 23: ...lter is applied to accentuate the high audio frequencies The Si4734 35 incorporates a de emphasis filter which attenuates high frequencies to restore a flat frequency response Two time constants are u...

Страница 24: ...he Si4734 35 is performing the seek tune function the crystal oscillator may experience jitter which may result in mistunes false stops and or lower SNR For best seek tune results Silicon Laboratories...

Страница 25: ...tions the control word is followed by a delay of one half SCLK cycle for bus turn around Next the Si4734 35 will drive the 16 bit read data word serially on SDIO changing the state of SDIO on each ris...

Страница 26: ...is idle Putting the device in power down mode will disable analog and digital circuitry while keeping the bus active 4 20 Programming with Commands To ease development time and offer maximum customiz...

Страница 27: ...cts the FM tuning frequency 0x21 FM_SEEK_START Begins searching for a valid frequency 0x22 FM_TUNE_STATUS Queries the status of previous FM_TUNE_FREQ or FM_SEEK_START command 0x23 FM_RSQ_STATUS Querie...

Страница 28: ...30 kHz 0x001E 0x1200 FM_RSQ_INT_ SOURCE Configures interrupt related to RSQ metrics 0x0000 0x1201 FM_RSQ_SNR_HI_ THRESHOLD Sets high threshold for SNR interrupt 0x007F 0x1202 FM_RSQ_SNR_LO_ THRESHOLD...

Страница 29: ...The bigger the number the higher the max attenuation level Default value is a slope of 2 0x0002 0x3302 AM_SOFT_MUTE_MAX_ ATTENUATION Sets maximum attenuation during soft mute dB Set to 0 to dis able...

Страница 30: ...irectly to battery 12 GND PAD GND Ground Connect to ground plane on PCB 13 ROUT Right audio line output in analog output mode 14 LOUT Left audio line output in analog output mode 15 DOUT Digital outpu...

Страница 31: ...ting Temperature Si4734 B20 GM AM FM SW LW Broadcast Radio Receiver QFN Pb free 20 to 85 C Si4735 B20 GM AM FM SW LW Broadcast Radio Receiver with RDS RBDS QFN Pb free 20 to 85 C Note Add an R at the...

Страница 32: ...Firmware Revision 20 Firmware Revision 2 0 Line 2 Marking Die Revision B Revision B Die TTT Internal Code Internal tracking code Line 3 Marking Circle 0 5 mm Diameter Bottom Left Justified Pin 1 Iden...

Страница 33: ...16 Package Dimensions Symbol Millimeters Symbol Millimeters Min Nom Max Min Nom Max A 0 50 0 55 0 60 f 2 53 BSC A1 0 00 0 02 0 05 L 0 35 0 40 0 45 b 0 20 0 25 0 30 L1 0 00 0 10 c 0 27 0 32 0 37 aaa 0...

Страница 34: ...34 Rev 1 0 10 PCB Land Pattern Si4734 35 QFN Figure 15 illustrates the PCB land pattern details for the Si4734 35 GM Table 17 lists the values for the dimensions shown in the illustration Figure 15 PC...

Страница 35: ...sk Design 1 All metal pads are to be non solder mask defined NSMD Clearance between the solder mask and the metal pad is to be 60 m minimum all the way around the pad Notes Stencil Design 1 A stainles...

Страница 36: ...e AN388 Universal Evaluation Board Test Procedure AN389 Si473x EVB Quick Start Guide Si47xx Customer Support Site http www mysilabs com This site contains all application notes evaluation board schema...

Страница 37: ...3 on page 7 Updated Table 8 Digital Audio Interface Characteristics on page 11 Updated Table 9 FM Receiver Characteristics1 2 on page 12 Updated Table 10 64 75 9 MHz Input Frequency FM Receiver Chara...

Страница 38: ...for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation or guar...

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