Silicon Laboratories SI4734-B20, Руководство по эксплуатации продукта

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S i 4 7 3 4 / 3 5 - B 2 0
10 Rev. 1.0
Figure 6. SPI Control Interface Write Timing Parameters
Figure 7. SPI Control Interface Read Timing Parameters
Table 7. SPI Control Interface Characteristics
(V
DD
= 2.7 to 5.5 V, V
IO
= 1.5 to 3.6 V, T
A
= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
SCLK Frequency f
CLK
0 — 2.5 MHz
SCLK High Time t
HIGH
25 — — ns
SCLK Low Time t
LOW
25 — — ns
SDIO Input, SEN to SCLK
↑
Setup t
S
15 — — ns
SDIO Input to SCLK
↑
Hold t
HSDIO
10 — — ns
SEN Input to SCLK
↓
Hold t
HSEN
5 — — ns
SCLK
↓
to SDIO Output Valid t
CDV
Read 2 — 25 ns
SCLK
↓
to SDIO Output High Z t
CDZ
Read 2 — 25 ns
SCLK, SEN, SDIO, Rise/Fall time
t
R
, t
F
— — 10 ns
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK
70%
30%
SEN
70%
30%
SDIO
C7 C0
70%
30%
t
S
C6
–C1
Control Byte In 8 Data Bytes In
D7 D6
–D1
D0
t
S
t
HSDIO
t
HIGH
t
LOW
t
HSEN
t
F
t
R
Bus
Turnaround
SCLK
70%
30%
SEN
70%
30%
SDIO
70%
30%
t
HSDIO
Control Byte In
C7 C0 C6
–C1
t
S
t
HSEN
t
S
t
CDZ
t
CDV
16 Data Bytes Out
(SDIO or GPO1)
D7 D6
–D1
D0