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Si4421

Evaluation Board with Resonant PCB Antenna (BIFA)

Schematics

* See values in the table

CS1

SSI

TP1

FFS

SEL SC

FFE VD

1
2
3

JP1

TP3

SDI

SCK

NSEL

SDO

NIRQ

FSK/DATA/NFFS

DCLK/CFIL

NINT/VDI

XTL/REF

CLK

VSS

RF2

RF1

VDD

ARSSI

NRES

IC1

ARSSI

RESET

SDI

SCK

SEL

SDO

IRQ

DATA

DCLK

DTO

CLKIN

VDI

CON40-0

100pF

10nF

GND

10M

10nF

GND

2.2uF

IA4421

10k

100k

10k

Note:

Components R5 to R8 and C6 are needed for connection to the ISM Chipset Development Kit load board (IA ISM-DK3) and are
not necessary in an application.

Frequency Dependent Component Values

Band

C3 [pF]

L1 [nH]

868 MHz

Dual (868/915 MHz)

47/33

915 MHz

Содержание SI4421

Страница 1: ...To minimize the system cost the Si4421 can provide a clock signal for the microcontroller avoiding the need for two crystals For low power applications the Si4421 supports low duty cycle operation bas...

Страница 2: ...erers Baseband Filters The receiver bandwidth is selectable by programming the bandwidth BW of the baseband filters This allows setting up the receiver according to the characteristics of the signal t...

Страница 3: ...eshold level The detector circuit has 50 mV hysteresis Wake Up Timer The wake up timer has very low current consumption 1 5 A typical and can be programmed from 1 ms to several days with an accuracy o...

Страница 4: ...gital filter used FIFO not used CFIL AIO External data filter capacitor connection Analog filter used 7 FFIT DO FIFO interrupt active high In FIFO mode when bit ef is set in Configuration Setting Comm...

Страница 5: ...ns Pin Name Internal connection 1 SDI 2 SCK 3 nSEL PAD 1 5k VSS VDD 4 SDO 5 nIRQ FSK DATA 6 nFFS DLCK CFIL 7 FFIT 8 CLK PAD 10 VSS VDD XTL 9 REF Pin Name Internal connection 10 nRES 11 VSS 12 RF2 13 R...

Страница 6: ...Si4421 PIN6 Logic Diagram FSK DATA nFFS PIN10 Logic Diagram nRES I O Note These pins can be left floating 6...

Страница 7: ...ng Band MHz C1 C2 C3 433 2 2 F 10nF 220pF 868 2 2 F 10nF 47pF 915 2 2 F 10nF 33pF Property C1 C2 C3 SMD size A 0603 0603 Dielectric Tantalum Ceramic Ceramic Pin Function vs Operation Mode Mode Bit set...

Страница 8: ...DD and VSS 25 25 mA ESD Electrostatic discharge with human body model 1000 V Tst Storage temperature 55 125 o C Tld Lead temperature soldering max 10 s 260 o C Recommended Operating Range Symbol Param...

Страница 9: ...pd Standby current Sleep mode All blocks disabled 0 3 1 A Ilb Low battery voltage detector current consumption 0 5 1 7 A Iwt Wake up timer current consumption 1 5 3 5 A Ix Idle current Crystal oscilla...

Страница 10: ...s Pmin Receiver Sensitivity BER 10 3 BW 67 kHz BR 1 2 kbps 868 MHz Band Note 3 110 dBm AFCrange AFC locking range fFSK FSK deviation in the received signal 0 8 fFSK IIP3inh Input IP3 In band interfere...

Страница 11: ...TX FSK bit rate TX data connected to the FSK input 256 kbps dffsk FSK frequency deviation Programmable in 15 kHz steps 15 240 kHz AC Characteristics Turn on Turnaround timings Symbol Parameter Conditi...

Страница 12: ...Antenna BIFA on page 41 for details Note 6 Optimal antenna admittance impedance Si4421 Yantenna mS Zantenna Ohm Lantenna nH 433 MHz 2 j5 9 52 j152 62 868 MHz 1 2 j11 9 7 8 j83 15 4 915 MHz 1 49 j12 8...

Страница 13: ...errupt request IT for the microcontroller by pulling the nIRQ pin low on the following events The TX register is ready to receive the next byte RGIT The RX FIFO has received the preprogrammed amount o...

Страница 14: ...to p0 12 PLL Setting Command CLK out buffer speed dithering PLL bandwidth ob1 to ob0 ddit dly bw0 13 Transmitter Register Write Command TX data register write t7 to t0 14 Wake Up Timer Command Wake up...

Страница 15: ...uffer The ebb es and ex bits are provided to optimize the TX to RX or RX to TX turnaround time The RF frontend consist of the LNA low noise amplifier and the mixer The synthesizer block has two main c...

Страница 16: ...more clock pulses are provided This ensures that the microcontroller can switch itself to low power consumption mode In order to use this feature a Status Read Command page 27 must be issued before t...

Страница 17: ...am in receive mode is determined by the 7 bit parameter R bits r6 to r0 and bit cs BR 10000 29 R 1 1 cs 7 kbps In the receiver set R according to the next function R 10000 29 1 cs 7 BR 1 where BR is t...

Страница 18: ...resent it will go low when all the three input signals are low Medium mode The VDI signal will be active when the CR_LOCK signal and either the DRSSI or the DQD signal is high The valid data indicator...

Страница 19: ...ode slow attack and slow release 12 to 16 bit preamble is recommended Using the slow mode requires more accurate bit timing see Data Rate Command page 17 Bit 4 s Select the type of the data filter s F...

Страница 20: ...meter can be calculated with the following formula DQDpar 4 x deviation TX RXoffset bit rate It should be larger than 4 because otherwise noise might be treated as a valid FSK signal The maximum value...

Страница 21: ...mand Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 B000h With this command the controller can read 8 bits from the receiver FIFO Bit 6 ef must be set in Configuration S...

Страница 22: ...uency offset Two measurement cycles can compensate 80 and three measurement cycles can compensate 92 The ATGL bit in the status register can be used to determine when the actual measurement cycle is f...

Страница 23: ...th cases 3a and 3b when the VDI indicates poor receiving conditions VDI goes low the output register is automatically cleared Use this drop offset mode when the receiver communicates with more than on...

Страница 24: ...erformance bw0 Max bit rate kbps Phase noise at 1MHz offset dBc Hz 0 86 2 107 1 256 102 Note POR default settings of the register were carefully selected to cover almost all typical applications When...

Страница 25: ...r a short period of time and checks if there is a valid FSK transmission in progress FSK transmission is detected in the frequency range determined by Frequency Setting Command page 17 plus and minus...

Страница 26: ...0 C000h The 4 bit parameter v3 to v0 represents the value V which defines the threshold voltage Vlb of the detector Vlb 2 25 V 0 1 V Clock divider configuration d2 d1 d0 Clock Output Frequency MHz 0 0...

Страница 27: ...flow Cleared after Status Read Command EXT Logic level on interrupt pin pin 16 changed to low Cleared after Status Read Command LBD Low battery detect the power supply voltage is below the pre program...

Страница 28: ...led in the Power Management command WKUP wake up timer interrupt This interrupt event occurs when the time specified by the Wake Up Timer Command page 25 has elapsed Valid only when the ew bit is set...

Страница 29: ...nterrupts Before freezing the microcontroller code a thorough testing must be performed in order to make sure that all interrupt sources are handled before putting the radio device to low power consum...

Страница 30: ...time The nIRQ pulse shows that the first 8 bits the first byte by default 0xAA has transmitted There are still 8 bits in the transmit register g The microcontroller recognizes the interrupt and write...

Страница 31: ...cked out by the SCK Set the FIFO IT level to 1 In this case as long as FFIT indicates received bits in the FIFO the controller may continue to take the bits away When FFIT goes low no more bits need t...

Страница 32: ...rature drift and aging can thus be determined from the maximum allowable local oscillator frequency error Whenever a low frequency error is essential for the application it is possible to pull the cry...

Страница 33: ...ment process itself will change the reference frequency Since the carrier frequencies are derived from the reference frequency having identical reference frequencies and nominal frequency settings at...

Страница 34: ...the power glitch detection circuit is disabled There can be spikes or glitches on the Vdd line if the supply filtering is not satisfactory or the internal resistance of the power supply is too high I...

Страница 35: ...t is very important to keep the Vdd line as smooth as possible Noise or periodic disturbing signal superimposed the supply voltage may prevent the part getting out from reset state To avoid this pheno...

Страница 36: ...witched off FSK deviation 45 kHz Vdd 2 7 V Measured according to the descriptions in the ETSI Standard EN 300 220 1 v2 1 1 2006 01 Final Draft section 9 The ETSI limit given in the figure is drawn by...

Страница 37: ...eband bandwidth BW and transmitter deviation frequency fFSK settings for different data rates supposing no transmit receive offset frequency If TX RX offset for example due to crystal tolerances have...

Страница 38: ...45 kHz BW 67 kHz 434 MHz 115 112 109 106 103 100 50 25 0 25 50 75 100 Celsius dBm 2 2V 2 7V 3 3V 3 8V Receiver Sensitivity over Ambient Temperature 868 MHz 2 4 kbps fFSK 45 kHz BW 67 kHz 868 MHz 115 1...

Страница 39: ...pF C10 pF C11 pF C3 pF 434 18 47 390 18 5 2 7 2 7 220 220 868 3 9 18 100 3 9 2 7 1 2 1 8 47 47 915 3 6 16 100 3 6 2 7 1 2 1 8 33 33 Recommended Component Types Part number Component Manufacturer 434M...

Страница 40: ...uency 3 The dielectric type should be C0G and the resonant frequency should be similar if components from alternative vendor used 4 The values are valid for 1 5mm thick FR4 PCB If thinner board used t...

Страница 41: ...REF 9 CLK 8 VSS 11 RF2 12 RF1 13 VDD 14 ARSSI 15 NRES 10 IC1 CLK_OUT R6 R7 R5 R8 ARSSI RESET RESET SDI SDI SCK SCK SEL SEL SDO SDO IRQ IRQ DATA DATA DATA DATA DCLK DCLK DCLK DTO DTO CLKIN CLKIN VDI VD...

Страница 42: ...Si4421 PCB Layout Antenna designed for 868 915 MHz band Top View Bottom View 42...

Страница 43: ...0 0 0 3 0 9 1 0 b b1 0 19 0 22 0 25 0 007 0 009 0 010 8 0 0 0 4 0 0 0 0 2 0 9 0 0 c 6 0 0 0 4 0 0 0 6 1 0 9 0 0 1 c D 4 90 5 00 5 10 0 193 0 197 0 201 e E E1 4 30 4 40 4 50 0 169 0 173 0 177 L 0 50 0...

Страница 44: ...missions and disclaims responsibility for any consequences resulting from the use of information included herein Additionally Silicon Laboratories assumes no responsibility for the functioning of unde...

Страница 45: ...Si4421 45...

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