Silicon Laboratories ISOMODEM Si2401, Руководство пользователя

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Si2401
20 Preliminary Rev. 0.9
Fast Connect
In modem applications that require fast connection
times, it is possible to reduce the length of the
handshake.
Additional modem handshaking control can be adjusted
through the registers shown in Table 11. These registers
are most useful if the user has control of both the
originating and answering modems.
When the fast connect settings are used, there may be
unintended data received initially.The host must tolerate
these bytes.
Clock Generation Subsystem
The Si2401 contains an on-chip clock generator. Using
a single master clock input, the Si2401 can generate all
modem sample rates necessary to support V.22bis,
V.22/Bell212A, and V.21/Bell103 standards and a
9.6 kHz rate for audio playback. Either a 27 MHz or
4.9152 MHz clock on XTALI or a 4.9152 MHz crystal
across XTALI and XTALO form the master clock for the
Si2401. This clock source is sent to an internal phase-
locked loop (PLL) that generates all necessary internal
system clocks. The PLL has a settling time of ~1 ms.
Data on RXD should not be sent to the device prior to
settling of the PLL. By default, the Si2401 assumes a
4.9152 MHz clock input. If a 27 MHz clock on XTALI is
used, a pulldown resistor <10 k
Ω
must be placed
between GPIO4 (Si2401, pin 11) and GND.
Table 11. V.22/Bell212 Handshaking Control Registers
Register Name Function Units Default Fast
Connect
S1E TATL Transmit Answer Tone Length 1 s 0x03 00
S1F ATTD Answer Tone to Transmit Delay 5/3 ms 0x2D 00
S20 UNL Unscrambled Ones Length—V.22 5/3 ms 0x5D 00
S21 TSOD Transmit Scrambled Ones Delay—V.22 53.3 ms 0x09 00
S22 TSOL Transmit Scrambled Ones Length—V.22 5/3 ms 0xA2 00
S23 VDDL V.22/22b Data Delay Low 5/3 ms 0xCB 00
S24 VDDH V.22/22b Data Delay High (256) 5/3 ms 0x08 00
S34 TASL Answer Tone Length
(only used in S1E [TATL] = 0x00) 5/3 ms 0x5A F0
S35 RSOL Receive V.22 Scrambled Ones Length 5/3 ms 0xA2 00