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Silicon Laboratories AN725, Руководство пользователя

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Silicon Laboratories AN725 Скачать руководство пользователя страница 24

A N 7 2 5

24

Rev. 0.1

In constant contrast mode, the VLCD voltage is held constant at all times, regardless of the voltage on VBAT. When
VBAT is above the threshold set by the VBMTH field, the LCD charge pump regulates to the contrast level set by
the CTRST field using a variable resistor. When VBAT reaches the threshold, the charge pump enables
automatically to keep VLCD at the desired value. This mode results in the highest power consumption, but may be
required by some system and LCD architectures.

Figure 14. LCD0 Constant Contrast Mode

In auto-bypass contrast mode shown in Figure 15, the VLCD voltage is held constant and tracks the VBAT voltage
below the threshold. When VBAT is above the threshold voltage set by VBMTH, VLCD regulates to the
programmed contrast voltage (CTRST) using a variable resistor between VBAT and VLCD. When VBAT reaches
the monitor threshold, the controller automatically enters bypass mode and powers VLCD directly from VBAT. The
charge pump is always disabled in this mode, and the threshold and contrast levels do not have to be set to the
same value, as shown in Figure 16.

Figure 15. LCD0 Auto-Bypass Contrast Mode

Figure 16. LCD0 Auto-Bypass Contrast Mode with Different Threshold and Voltage Settings

For lowest power consumption, applications should use bypass or minimum contrast modes whenever possible.

VBAT

VLCD

VBAT

VLCD

VBAT

VLCD

CTRST

VBMTH

Содержание AN725

Страница 1: ...ted systems This document addresses each of these features and provides guidelines for achieving low power consumption in a variety of configurations and applications 2 Key Points This key topics of this document are as follows How to reduce active mode time and power consumption How to reduce low power mode power consumption Measuring the low power modes on an SiM3L1xx MCU card General power savi...

Страница 2: ... help move data without core intervention This reduces overall power consumption by removing the power consumed during flash accesses Additionally since the Cortex M3 is a load store architecture where data is loaded into and out of registers only multiple instructions are required to move data from one area of memory to another so the DMA and DTM may be faster than data moves by the core dependin...

Страница 3: ...d flash access frequency at AHB frequencies above 40 MHz The APB clock is equal to the AHB clock when the APB is enabled As shown by the data the flash access frequency SPMD has a direct effect on the code that includes branches since the core stalls when waiting for the new instructions resulting in reduced power consumption This means that it may be more efficient to run at a faster frequency wi...

Страница 4: ...V to reduce the amount of excess power consumed by these circuits with some buffer to ensure correct operation When the digital or memory LDOs are sourced from the dc dc converter adaptive voltage scaling can also allow the LDOs to track the dc dc output voltage to utilize the higher efficiency of the dc dc converter and reduce the losses in the regulators Figure 3 Reducing Power Consumption with ...

Страница 5: ...er There are three ranges of operation for the dc dc converter corresponding to three different load sizes 1 Loads less than 5 mA 2 Loads between 5 and 15 mA 3 Loads greater than 15 mA When operating with loads less than 5 mA the dc dc converter is most efficient when configured for light loads 1 Power switch size set to 0 PSMD 0 2 Asynchronous mode enabled ASYNCEN 1 3 Minimum pulse width set to 4...

Страница 6: ...ill be active and the core will halt for a period of time then the load may be less than 5 mA Firmware can adjust the dc dc converter appropriately during this period If the core is fetching instructions from flash at full speed and executing a math routine then switching to the high load configuration will yield lower power consumption For extremely light loads less than 2 3 mA the dc dc converte...

Страница 7: ...t that wakes the device from PM2 must be of a sufficient priority to be recognized by the core It is recommended to perform both a DSB Data Synchronization Barrier and an ISB Instruction Synchronization Barrier operation prior to the WFI to ensure all bus access is complete 5 1 4 Power Mode 3 Fast Wake Power Mode 3 Fast Wake occurs when all the clocks are stopped except for the LFOSC0 or RTC0TCLK ...

Страница 8: ...ialized VBAT divided by 2 low power mode charge pump that can power some internal modules while in PM8 to save power The fully operational functions in this mode are LPTIMER0 RTC0 UART0 running from RTC0TCLK port match advanced capture counter and the LCD controller This mode provides the lowest power consumption for the device but requires an appropriate wake up source or reset to exit The availa...

Страница 9: ...M3CN WFI or WFE instruction Requires a wake up source or reset defined by the PMU Power Mode 4 PM4 Core operating at slower speed Code executing from flash Set the AHB clock to a slower source Set the AHB clock to a faster source Power Mode 5 PM5 Core operating at slower speed Code executing from RAM Set the AHB clock to a slower source Execute code from RAM Set the AHB clock to a faster source or...

Страница 10: ...e three shorting blocks from J7 3 Remove the JP2 Imeasure shorting block and put a multimeter across positive side on the bottom pin 4 Move the VBAT Sel switch SW2 to the middle 3 3 V_VREG position 5 Move the VIO Sel SW8 and VIORF Sel SW9 switches to the bottom VBAT position 6 Connect the 9 V power adapter to POWER J6 7 Download the code to the board 8 Remove the debug adapter connection 9 Measure...

Страница 11: ... 7 Optional Instead of a battery connect the positive terminal of a bench power supply to the positive terminal of the multimeter the negative terminal of the power supply to the MCU card ground and the negative terminal of the multimeter to the top pin of the Imeasure jumper JP2 This configuration will prevent any circuitry on the board from interfering with the power measurement 8 Download the c...

Страница 12: ... Hardware Setup 2 Open the AN725_PowerModes_0_and_4 example in either Keil µVision or the Precision32 IDE 3 Select the desired settings using the defines at the top of the file There is a set of defines for each data sheet specification 4 Compile and download the code to the device 5 Disconnect the USB Debug Adapter 6 Reset the device 7 Measure the power consumption of the device 5 2 3 Configuring...

Страница 13: ...0 etc and speed for both AHB and APB clocks 3 Select the desired adaptive voltage scaling settings using the LDO module 4 Optional Disable the retention mode of any enabled RAM banks 5 Set the pins in the lowest power configuration for this mode 6 Disable all unused peripherals 7 Disable the clocks to all unused peripherals 8 Jump to code in RAM 9 Optional Disable the AHB clock to the flash contro...

Страница 14: ... to all unused peripherals 11 Jump to code in RAM 12 Execute the DSB Data Synchronization Barrier ISB Instruction Synchronization Barrier and WFI Wait for Interrupt or WFE Wait for Event instructions For SiM3L1xx devices WFI and WFE have the same behavior To measure the data sheet numbers using an SiM3L1xx MCU Card and the AN725_PowerModes_2_and_6 example 1 Configure the SiM3L1xx MCU Card accordin...

Страница 15: ...ll of the LDOs in low bias mode 11 Clear the PMU wakeup flags 12 Disable the SysTick timer 13 Disable all unused peripherals 14 Disable the clocks to all unused peripherals 15 Execute the DSB ISB and WFI or WFE instructions For SiM3L1xx devices WFI and WFE have the same behavior To measure the data sheet numbers using an SiM3L1xx MCU Card and the AN725_PowerMode3_Fast_Wake example 1 Configure the ...

Страница 16: ...0 ACCTR0 LCD0 etc 10 Optional If using the RTC in low frequency oscillator mode enable the RTC0 module using the steps in the Reference Manual If using the RTC in crystal mode the recommended initialization sequence is a Disable RTC0 automatic gain control AGC and enable the bias doubler b Set up the RTC0 in crystal mode using the list of steps in the Reference Manual c Optional Enable the charge ...

Страница 17: ... top of the file 4 Compile and download the code to the device 5 Disconnect the USB Debug Adapter 6 Connect PB0 2 to PB1 5 using a short wire and the J21 and J22 headers 7 Power down the board 8 Power up the board This will cause a power on reset that will clear the settings of some modules i e PMU 9 Press PB1 7 to place the device in PM8 The PB1 5 LED will turn off 10 Measure the power consumptio...

Страница 18: ...1 Charge Pump Output Voltage The value of RCPLOAD depends on the output drive setting field CPLOAD in the PMU module and the clock selected by the RTC0 module as shown in Table 3 All circuitry powered by the charge pump operates correctly at VCP voltages greater than or equal to 0 95 V Thus for a given charge pump load current Equation 2 must be true Equation 2 Charge Pump Output Voltage Requireme...

Страница 19: ... a glitch from the oscillators due to the sudden change in the charge pump output may disturb the logic s operation 5 3 2 Measuring PM8 Charge Pump Current To measure the charge pump load current use CMP0 to detect the output voltage of the charge pump during PM8 This output voltage combined with an ADC measurement of the VBAT value can help estimate the present charge pump load in PM8 To do this ...

Страница 20: ...m is the drive impedance for CPLOAD 1 Putting these equations together and solving for ILOAD gives Equation 4 Minimum Charge Pump Output Voltage to Increase Drive Impedance Equation 4 provides the minimum VCP value for the present CPLOAD setting that allows CPLOAD to be reduced by 1 without the output dropping below 0 95 V Using this equation the CMP0 DAC setting that corresponds to this equation ...

Страница 21: ...en 0 and 3 V for example which results in an amplitude of 3 to 3 V on the segment depending on the phase of the segment and common waveforms Figure 9 shows an example of the common waveforms for 4 mux mode To turn on a segment the controller drives the segment to 3 V or 0 V when the common is driven to 0 V or 3 V which leads to 3 V on the segment To turn a segment off the controller drives the seg...

Страница 22: ...tential depending on the phase Overall this reset waveform scheme reduces the current load of an LCD by 40 regardless of the number of segments in the display Power conscious applications using an LCD should enable this feature RPHEN 1 and set the number of RTC0 clocks to reset the segment RPHMD field using the LCD0 SEGCONTROL register Generally a RPHMD value of 2 provides significant power saving...

Страница 23: ...tage is relatively constant Figure 11 LCD0 Bypass Contrast Mode In minimum contrast mode shown in Figure 12 the VLCD voltage will track the VBAT voltage to a minimum level set by the VBAT monitor threshold VBMTH When VBAT is equal to this voltage VLCD will switch to the contrast level set by the CTRST field The threshold and contrast voltages do not have to be set to the same level as shown in Fig...

Страница 24: ...e VLCD voltage is held constant and tracks the VBAT voltage below the threshold When VBAT is above the threshold voltage set by VBMTH VLCD regulates to the programmed contrast voltage CTRST using a variable resistor between VBAT and VLCD When VBAT reaches the monitor threshold the controller automatically enters bypass mode and powers VLCD directly from VBAT The charge pump is always disabled in t...

Страница 25: ...8 5 5 1 Adjusting the Stack Pointer with Keil µVision With Keil µVision projects the stack location can be controlled in the scatterfile The default linker_sim3l1xx_arm sct scatterfile can be found in the C SiLabs 32bit si32 x y z si32Hal sim3l1xx directory where x is the major si32HAL version y is the minor version and z is the trivial version Inside the scatterfile ARM_LIB_STACK SI32_MCU_RAM_BAS...

Страница 26: ...Build Settings Tool Settings tab MCU Linker Target and input the desired stack offset into the Stack offset field This offset will occur from the top address of RAM and the value must be a multiple of 4 Figure 17 shows this dialog in the Precision32 IDE Figure 17 Using the Precision32 IDE to Select the Project Library After changing either the custom linker script or IDE settings clean and rebuild...

Страница 27: ... peripheral registers will be disabled Disabling the module explicitly DCDCEN 0 for the DCDC0 module for example will ensure the module does not draw extra power in the low power mode 6 3 Biases In addition to peripherals disable any unneeded bias sources in the device before entering the low power mode These biases draw current to provide voltage references inside the chip One example of a bias i...

Страница 28: ...s not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in...

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