manualshive.com logo in svg

SIGNALCORE SC5520A, Руководство по оборудованию

Поделиться
Скачать
SIGNALCORE SC5520A Скачать руководство пользователя страница 12

 

©2020 

Rev 1.1

 

11 

Theory and Operation 

3

 

Theory and Operation 

The UHFS module is an instrument-grade, high performance synthesizer with easy to program register-
level control. It functions as a standard synthesized CW source with the added capability of a sweep/list 
mode that makes it ideal for applications ranging from automated test systems to telecommunication 
equipment to scientific research labs. Being small and modular, it is the ideal solution for system 
integration applications that require a high performance RF source. In addition, it could be used as a 
general-purpose lab source. Figure 2 shows the block diagram of the device, and the following sub-
sections provide details of its operation. 

 

Figure 2. UHFS block diagram 

 

RF Generation 

The UHFS is a 160 MHz to 40 GHz low phase noise, low harmonics, low sub-harmonics, and low spur 
synthesizer that uses a hybrid synthesizer architecture comprising of phase lock loops, harmonic 
generation, and a DDS functions. Coarse tuning is accomplished by PLL and harmonic generators, while 
fine tuning is accomplished with the variable modulus DDS, providing exact frequency generation with 
resolution of 1 Hz. Isolation between the internal oscillators, their mixed IF products, harmonics, and 
inter-modulation products is accomplished by internal EMI sealed cavities, resulting in improved the 
overall phase noise performance and reduction of spurious signal content of this compact size frequency 
synthesizer. Synthesized signals are either referenced to an internal 10 MHz OCXO clock, or an external 
10 MHz reference source. 

 

Amplitude Control 

The output level of the UHFS is controlled through the use of a voltage variable gain amplifier (VVA) and a 
step attenuation, the VVA is control via a level DAC. The level is automatically controlled by the device 
based on the user level requirement. However, the user may choose to override these settings by 
excessing these components, both the leveling DAC and the step attenuator can be control by software 
via registers.  

N

Fine Step 

Gen

REF 
IN

REF 
OUT

RF1 
OUT

10 GHz - 

20 GHz 

Gen

Harmonic 
St ep  Gen

VCXO

100  MHz

OCXO

10 MHz

FracN 

St ep  Gen

2

Subharmonic

Filt ers

ATT

LEVEL 
DAC

Содержание SC5520A

Страница 1: ... 2020 SignalCore Inc All Rights Reserved Hardware Manual SC5520A SC5521A UHFS 160 MHz to 40 GHz CW Signal Source Rev 1 1 www signalcore com ...

Страница 2: ...ing the UHFS Device 6 Front Interface Indicators and Connectors 7 Signal Connections 8 Device LED Indicators 8 Communication and Supply Connection 9 Mini USB Connection 10 Reset Button Pin Hole 10 3 Theory and Operation 11 RF Generation 11 Amplitude Control 11 Reference Mode 12 Computational Time 12 Internal EEPROM 12 Modes of RF Generation 12 Sweep Function 12 List Function 13 Sweep Direction 13 ...

Страница 3: ...rved 21 Register 0x0C LIST_BUFFER_POINTS 3 Bytes 21 Register 0x0D LIST_BUFFER_WRITE 7 Bytes 22 Register 0x0E LIST_BUF_MEM_TRNSFER 1 Byte 22 Register 0x0F LIST_SOFT_TRIGGER 1 Byte 22 Register 0x10 RF_FREQUENCY 7 Bytes 23 Register 0x11 RF_LEVEL 3 Bytes 23 Register 0x12 RF_ENABLE 1 Byte 23 Register 0x13 RF_PHASE 7 Bytes 23 Register 0x14 AUTO_LEVEL_DISABLE 1 Byte 24 Register 0x15 Reserved 1 Byte 24 Re...

Страница 4: ...TCH_DAC_VALUE 1 Byte 8 Bytes 31 Register 0x26 SERIAL_OUT_BUFFER 31 5 Communication Interfaces 33 Communication Data Format 33 USB Interface 33 Control Transfer 33 Bulk Transfer 33 SPI Interface 34 Writing the SPI Bus 35 Reading the SPI Bus 35 RS232 Interface 36 Writing to the Device Via RS232 36 Reading from the Device Via RS232 37 PXI 37 Setting Up the PCI to Serial Bridge 37 Writing to the Devic...

Страница 5: ...IGNALCORE INCORPORATED SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER SIGNALCORE INCORPORATED WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of SignalCore Incorporated will apply regardless of the form of action whether in contract ...

Страница 6: ...tained in all of the homogeneous materials for this product is below the limit requirement in SJ T11363 2006 An X indicates that the particular hazardous substance contained in at least one of the homogeneous materials used for this product is above the limit requirement in SJ T11363 2006 CE European Union EMC Declaration The European Conformity CE marking is affixed for products which may cause o...

Страница 7: ...tic packaging bags to prevent damage from electrostatic discharge ESD Under certain conditions an ESD event can instantly and permanently damage several of the components found in SignalCore products Therefore to avoid damage when handling any SignalCore hardware you must take the following precautions 1 Ground yourself using a grounding strap or by touching a grounded metal object 2 Touch the ant...

Страница 8: ...ling options cannot be provided A cooling plan is sufficient when the SC5520A and SC5521A on board temperature sensors indicate a rise of no more than 20 C above ambient temperature under normal operating conditions Front Interface Indicators and Connectors The SC5520A is a PXIe based RF signal source with all RF connectors located on the front face of the module Its control I O is via the back PX...

Страница 9: ... gently clean inside the connector barrel and the external threads Do not mate connectors until the alcohol has completely evaporated Excess liquid alcohol trapped inside the connector may take several days to fully evaporate and may degrade measurement performance until fully evaporated Tighten all SMA connections to 5 in lb max 56 N cm max RF out This port outputs the tunable RF signal of the so...

Страница 10: ...f Communication and Supply Connection Figure 1 Power and Digital IO Connector Power and communication to the modules is provided through a rectangular connector from Samtec whose part number is TFM 115 01 L D RA It also serves as the digital connector interface for RS232 SPI trigger and other digital signals The pin definitions are listed in Table 3 Pinouts are different for different SignalCore p...

Страница 11: ... computers The pinout of this connector viewed from the front is shown in the following table Table 4 Pinout of the SC5521A USB communication connector PIN USB Function Description 1 VBUS Vcc 5 Volts 2 D Serial Data neg 3 D Serial Data pos 4 ID Not Used 5 GND Device Ground also tied to connector shell Reset Button Pin Hole Behind this pin hole is the reset button that is only available on the SC55...

Страница 12: ...ing is accomplished by PLL and harmonic generators while fine tuning is accomplished with the variable modulus DDS providing exact frequency generation with resolution of 1 Hz Isolation between the internal oscillators their mixed IF products harmonics and inter modulation products is accomplished by internal EMI sealed cavities resulting in improved the overall phase noise performance and reducti...

Страница 13: ...c leveling feature Internal EEPROM The UHFS contains an EEPROM whose memory space is divided into calibration and operating data spaces The calibration data space contains device information such as serial number hardware revision firmware revision and production date In addition this space holds the calibration data for frequency tuning and amplitude control The operating data space contains the ...

Страница 14: ...the onboard RAM it is not possible to have a pre calculated configuration parameters list that could be used to program the various functions of the device decreasing the setup time of the device for frequency change As a result for each frequency change the configuration parameters are dynamically computed This overhead computational time to handle the mathematics triggers timers and interrupts m...

Страница 15: ...on This can only be done through hardware triggering When hardware step triggering has started performing a software trigger or changing the RF mode to single fixed tone will take the device out of step trigger state before a cycle is completed Trigger Out Modes The device can be set to send out a high to low transition signal when the configuration of a frequency by the device is completed that i...

Страница 16: ...VE 0x02 7 0 Open Open Open Open Open Open Open Enable active LED SYNTH_MODE 0x03 7 0 Open Open Open Open Open Disable SS Loop gain Lock mode RF_MODE 0x04 7 0 Open Open Open Open Open Open Open Mode LIST_MODE_CONFIG 0x05 7 0 Trig out mode Trig out enable Return to start Step on trigger Hw trigger Saw Tri wave Sweep dir SSS mode LIST_START_FREQ 0x06 55 0 Frequency Word mHz 55 0 LIST_STOP_FREQ 0x07 5...

Страница 17: ...0x1C 7 0 Open Open Open Open Open Open Open Select Synth SET_ATTEN_DIRECT 0x1D 7 0 zero Atten value 6 0 0 5 dB LSB RESERVED 0x1E 7 0 RESERVED 0x1F 7 0 Each register from the table above is explained in detail in the following subsections Register 0x01 INITIALIZE 1 Byte This register allows the user to re initialize the device with current settings or to the power up state Bit Type Name Width Descr...

Страница 18: ...offset mode 1 WO Loop Gain 1 0 Normal loop gain for better close in phase noise 1 Low loop gain for better far out phase noise and spur suppression 2 WO Disable spur suppression 1 Only applies in harmonic offset mode see bit 0 0 The device automatically switches to fracN offset mode to avoid potentially large spurs due to intermodulation between the carrier and the harmonics of the reference clock...

Страница 19: ...S Mode 1 0 List mode Device gets its frequency points from the list buffer uploaded via the LIST_BUFFER_WRITE register 0x0D 1 Sweep mode The device computes the frequency points using the Start Stop and Step frequencies 1 WO Sweep Direction 1 0 Forward In the forward direction the sweeps start from the lowest start frequency or start at the beginning of the list buffer 1 Reverse In the reverse dir...

Страница 20: ... device will step to the next frequency on a trigger Upon completion of the number of cycles set by the LIST_CYCLE_COUNT register the device will exit from the stepping state and stop Further triggering will set the device back into the stepping state To exit the stepping state and stop before reaching the end of a cycle a software trigger must be sent or a change in the RF mode to single fixed to...

Страница 21: ...er than the stop frequency The Sweep Direction bit 1 of register 0x05 should be used to determine where the sweep should begin Register 0x08 LIST_STEP_FREQ 7 Bytes This register sets the list step frequency Bit Type Name Width Description 55 0 WO List Step Frequency 56 Sets the step frequency for a sweep Step size should not exceed the difference between the start and stop frequencies Register 0x0...

Страница 22: ...Unused 24 Set to zeros Register 0x0B Reserved Bit Type Name Width Description 7 0 WO Reserved 7 Register 0x0C LIST_BUFFER_POINTS 3 Bytes This register sets the number of frequency points to step through in the buffer list Bit Type Name Width Description 15 0 WO Number of Buffer Points 16 Sets the number of frequency points to step through in the buffer list The number must be equal to or less than...

Страница 23: ...55 1 at any time will terminate the write process and stops the pointer increment The value at which the pointer stops is the new count of list frequency points unless it is overwritten by register LIST_BUFFER_POINTS 55 WO Frequency or Amplitude 1 0 indicates that the bits 54 0 buffer is frequency 1 indicates that the buffer is amplitude Register 0x0E LIST_BUF_MEM_TRNSFER 1 Byte This register tran...

Страница 24: ... of dB To set to 10 25 dB write 1025 to this register 15 WO Sign bit 1 0 Positive number 1 Negative number 23 16 WO Unused 8 Zeros Register 0x12 RF_ENABLE 1 Byte This register enables and disables the RF1 output power Bit Type Name Width Description 0 WO RF1 Enable 1 0 Disables the output power 1 Enables the output power 7 1 WO Unused 7 Set all bits to zero Register 0x13 RF_PHASE 7 Bytes This regi...

Страница 25: ... zero Register 0x16 RF_STANDBY 1 Byte This register puts the RF1 channel into standby reducing power consumption Bit Type Name Width Description 0 WO RF1 Standby 1 1 Puts the RF1 channel into standby Standby powers down all circuitry associated with ch1 thus reducing power consumption 7 1 WO Unused 7 Set all bits to zero Register 0x17 REFERENCE_MODE 1 Byte This register tells the device to lock to...

Страница 26: ...Value 24 Set to zeros Register 0x1B STORE_DEFAULT_STATE 1 Byte This register stores the current configuration into memory Bit Type Name Width Description 7 0 WO Reserved 8 Set all bits to zero Calling this register will store the current configuration into memory On reset or power up these values are read from memory and set as the default values Register 0x1C SELF_SYNTH_CAL 1 Byte This register t...

Страница 27: ...est instruction byte Returned data length is always 8 bytes 64 bits with the first byte being the most significant MSB Not all 8 bytes are valid some have 7 some 4 and others 2 It is important that all 8 bytes are read in order to clear the interface buffers Table 7 Query Registers Register Name Register Address Serial Range Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FETCH_RF_PARAMETERS 0x20 ...

Страница 28: ... valid bytes 0x0A Current level DAC value 2 valid bytes is 4 bytes of a float format number for example float phase float read_in_unsigned_int 7 4 WO Unused 4 Set all bits to zero 63 0 RO Data 64 Data with varying sizes of unsigned type Register 0x21 GET_TEMPERATURE 1 Byte 8 Bytes Write to this register to query the device temperature Bit Type Name Width Description 7 0 WO Unused 8 Set all to zero...

Страница 29: ...0 HW trigger starts and stops the list 1 HW trigger steps the list points 27 RO List Config HW Trig 1 0 SW trigger 1 HW trigger 26 RO List Config Waveform Tri Saw 1 0 list steps start to stop then traces the steps back to start 1 list steps start to stop and returns immediately to start 25 RO List Config Sweep Dir 1 0 start to stop 1 stop to start 24 RO List Config SSS mode 1 0 uses list points ca...

Страница 30: ... level disable 1 0 power leveling enabled for every freq change 1 disabled 11 RO Operate device standby 1 1 standby enabled 10 RO Operate device accessed 1 1 device accessed 9 RO Operate loop_gain 1 0 normal 1 low loop gain 8 RO Operate lock_mode 1 0 harmonic 1 fracN 7 RO Unused 1 6 RO Pll_status ref_OCXO 1 1 the 10 MHz OCXO is locked 5 RO Pll_status ref_VCXO 1 1 the 100 MHz VCXO is locked 4 RO Pl...

Страница 31: ...d also to clear the output buffer 0 Obtain the product serial number 1 Obtain the hardware revision 2 Obtain the firmware revision 3 Obtain the manufacture date 7 3 WO Unused 5 31 0 RO data 32 Data for the requested parameter Product Serial Number 32 bit unsigned Hardware Revision typecast to 32 bit float Firmware Revision typecast to 32 bit float Manufacture Date unsigned 32 bit with following 31...

Страница 32: ...iption 0 WO DAC select 1 0 is high frequency synth ALC DAC value 1 is low frequency synth amplitude DAC value 7 1 WO Used 15 Zeros 15 0 RO DAC Value 16 Data 63 16 RO Invalid Data 48 Zeros Register 0x26 SERIAL_OUT_BUFFER Writing to this register only provides the 64 clock edges Reg 7 data bytes to transfer serial data from the device through SPI Other interfaces do not use this register Bit Type Na...

Страница 33: ...Rev 1 1 SC5520A SC5521A Hardware Manual SignalCore Inc 32 Section 2 Communication Interfaces ...

Страница 34: ...y is sent in 1000th of a Hertz so the data that represents the frequency is 12 000 000 000 000 milli Hertz 2 This number can be represented by a 64 bit unsigned long and in Hexadecimal is 0x 0000 0AE9 F7BC C000 The least 7 bytes are necessary to represent all frequencies allowable for this device so the MSB is used to hold the register address 3 A buffer needs to be 8 bytes for register RF_FREQUEN...

Страница 35: ... be asserted low for the entire duration of a register transfer Once a full transfer has been received the device will proceed to process the command and de assert low the SRDY pin The status of this pin may be monitored by the host because when it is de asserted low the device will ignore any incoming data The device SPI is ready when the previous command is fully processed and the SRDY pin is re...

Страница 36: ...n bytes depends on the register being targeted The first byte sent is the register address and subsequent bytes contain the data associated with the register As data from the host is being transferred to the device via the MOSI line data present on its SPI output buffer is simultaneously transferred back MSB first via the MISO line The data returned is invalid for configuration registers The follo...

Страница 37: ...gital IO connector selects the rate By default if the pin is pulled high or open the rate is set to 115200 at power up or upon HW reset When the pin is pulled low or grounded the rate is set to 57600 upon reset or power up Data bits The number of bits in the data is fixed at 8 Parity Parity is 0 zero Stop bits 1 stop bit Flow control 0 zero or none Only 3 wire RS232 is required since hardware flow...

Страница 38: ...ister information As with the configuration registers it is important that all data byte s write associated with the query registers are sent even if they are null All queries will return 8 bytes of data read with the first received byte being the most significant MSB Section 4 2 Query Registers provides the format details of the received data PXI The PXIe interface contains a high speed PCIe to S...

Страница 39: ...umber of configuration write bytes needed for each device register The first byte sent is the device register address followed by the most significant byte of the register s associated data When a device register is fully written that is all its data has been sent to the device it will return 1 byte This returned byte must be read by the host to clear the transfer buffer so that later received dat...

Страница 40: ... 2020 Rev 1 1 39 Revision Table Revision Table Revision Revision Date Description 0 1 11 26 2019 Document Created 1 0 2 26 2020 Initial Release 1 1 4 22 2020 Grammatical edits ...

Отзывы:

Нет отзывов

Бренды по названию

Популярные бренды

Загрузить еще бренды