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Serial Peripheral Interface (SPI)

This chapter describes the operation of the SiFive Serial Peripheral Interface (SPI) controller.

SPI Overview

The SPI controller supports master-only operation over the single-lane, dual-lane, and quad-
lane protocols. The baseline controller provides a FIFO-based interface for performing pro-
grammed I/O. Software initiates a transfer by enqueuing a frame in the transmit FIFO; when the
transfer completes, the slave response is placed in the receive FIFO.

In addition, a SPI controller can implement a SPI flash read sequencer, which exposes the
external SPI flash contents as a read/execute-only memory-mapped device. Such controllers
are reset to a state that allows memory-mapped reads, under the assumption that the input
clock rate is less than 100 MHz and the external SPI flash device supports the common Win-
bond/Numonyx serial read (

0x03

) command. Sequential accesses are automatically combined

into one long read command for higher performance.

The

fctrl

register controls switching between the memory-mapped and programmed-I/O

modes, if applicable. While in programmed-I/O mode, memory-mapped reads do not access the
external SPI flash device and instead return

0

immediately. Hardware interlocks ensure that the

current transfer completes before mode transitions and control register updates take effect.

SPI Instances in FE310-G003

FE310-G003 contains three SPI instances. Their addresses and parameters are shown in Table
63.

Table 63:

SPI Instances

Instance

Flash Controller

Address

cs_width

div_width

QSPI 0

Y

0x10014000

1

12

FE310-G003 Manual

© SiFive, Inc.

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Содержание FE310-G003

Страница 1: ...SiFive FE310 G003 Manual v1p1 SiFive Inc ...

Страница 2: ...ons of mer chantability fitness for a particular purpose and non infringement SiFive does not assume any liability rising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation indirect incidental spe cial exemplary or consequential damages SiFive reserves the right to make changes without further notice to any products...

Страница 3: ...ulation 11 1 10 I C 12 1 11 Debug Support 12 2 List of Abbreviations and Terms 13 3 E31 RISC V Core 15 3 1 Instruction Memory System 15 3 1 1 I Cache Reconfigurability 16 3 2 Instruction Fetch Unit 16 3 3 Execution Pipeline 16 3 4 Data Memory System 17 3 5 Atomic Memory Operations 17 3 6 Supported Modes 18 3 7 Physical Memory Protection PMP 18 3 7 1 Functional Description 18 3 7 2 Region Locking 1...

Страница 4: ...rogrammable Low Frequency Ring Oscillator LFROSC 31 6 8 Alternate Low Frequency Clock LFALTCLK 32 6 9 Clock Summary 32 7 Power Modes 34 7 1 Run Mode 34 7 2 Wait Mode 34 7 3 Sleep Mode 34 8 Interrupts 36 8 1 Interrupt Concepts 36 8 2 Interrupt Operation 37 8 2 1 Interrupt Entry and Exit 37 8 3 Interrupt Control Status Registers 38 8 3 1 Machine Status Register mstatus 38 8 3 2 Machine Trap Vector m...

Страница 5: ...tion 51 10 9 Error Device 52 11 One Time Programmable Memory OTP Peripheral 53 11 1 Memory Map 53 11 2 Programmed I O lock register otp_lock 54 11 3 Programmed I O Sequencing 55 11 4 Read sequencer control register otp_rsctrl 55 11 5 OTP Programming Warnings 56 11 6 OTP Programming Procedure 56 12 Always On AON Domain 57 12 1 AON Power Source 58 12 2 AON Clocking 58 12 3 AON Reset Unit 58 12 4 Pow...

Страница 6: ...og Interrupts wdogip0 65 14 Power Management Unit PMU 66 14 1 PMU Overview 67 14 2 Memory Map 67 14 3 PMU Key Register pmukey 68 14 4 PMU Program 69 14 5 Initiate Sleep Sequence Register pmusleep 70 14 6 Wakeup Signal Conditioning 70 14 7 PMU Interrupt Enables pmuie and Wakeup Cause pmucause 70 15 Real Time Clock RTC 72 15 1 RTC Count Registers rtccounthi rtccountlo 72 15 2 RTC Configuration Regis...

Страница 7: ...4 17 9 Baud Rate Divisor Register div 85 18 Serial Peripheral Interface SPI 87 18 1 SPI Overview 87 18 2 SPI Instances in FE310 G003 87 18 3 Memory Map 88 18 4 Serial Clock Divisor Register sckdiv 89 18 5 Serial Clock Mode Register sckmode 90 18 6 Chip Select ID Register csid 90 18 7 Chip Select Default Register csdef 91 18 8 Chip Select Mode Register csmode 91 18 9 Delay Control Registers delay0 ...

Страница 8: ...106 19 10 Generating Center Aligned Phase Correct PWM Waveforms 106 19 11 Generating Arbitrary PWM Waveforms using Ganging 108 19 12 Generating One Shot Waveforms 108 19 13 PWM Interrupts 108 20 Inter Integrated Circuit I C Master Interface 109 20 1 I C Instance in FE310 G003 109 21 Debug 110 21 1 Debug CSRs 110 21 1 1 Trace and Debug Register Select tselect 111 21 1 2 Trace and Debug Data Registe...

Страница 9: ...3 2 Debug ROM 0x800 0xFFF 116 21 3 3 Debug Flags 0x100 0x110 0x400 0x7FF 116 21 3 4 Safe Zero Address 116 21 4 Debug Interface 117 21 4 1 JTAG TAPC State Machine 117 21 4 2 Resetting JTAG Logic 117 21 4 3 JTAG Clocking 118 21 4 4 JTAG Standard Instructions 118 21 4 5 JTAG Debug Commands 118 22 References 119 FE310 G003 Manual SiFive Inc Page 7 ...

Страница 10: ... process This manual serves as an architec tural reference and integration guide for the FE310 G003 The FE310 G003 is compatible with all applicable RISC V standards and this document should be read together with the official RISC V user level privileged and external debug architecture specifications 1 1 FE310 G003 Overview Figure 1 shows the overall block diagram of the FE310 G003 A feature summa...

Страница 11: ...errupts con nected to the PLIC with 7 levels of priority UART 0 Universal Asynchronous Synchronous Transmitters for serial communication UART 1 Universal Asynchronous Synchronous Transmitters for serial communication QSPI 0 Serial Peripheral Interface QSPI 0 has 1 chip select sig nal 4 DQ lines SPI 1 Serial Peripheral Interface SPI 1 has 4 chip select signals 3 CS lines 2 DQ lines SPI 2 Serial Per...

Страница 12: ...as well as standard Mul tiply Atomic and Compressed RISC V extensions RV32IMAC The core is described in more detail in Chapter 3 1 3 Interrupts The FE310 G003 includes a RISC V standard platform level interrupt controller PLIC which supports 52 global interrupts with 7 priority levels The FE310 G003 also provides the standard RISC V machine mode timer and software interrupts via the Core Local Int...

Страница 13: ...ter Multiple universal asynchronous receiver transmitter UARTs are available and provide a means for serial communication between the FE310 G003 and off chip devices The UART peripherals are described in Chapter 17 1 8 Hardware Serial Peripheral Interface SPI There are 3 serial peripheral interface SPI controllers Each controller provides a means for serial communication between the FE310 G003 and...

Страница 14: ...ail in Chapter 20 1 11 Debug Support The FE310 G003 provides external debugger support over an industry standard JTAG port including 8 hardware programmable breakpoints per hart Debug support is described in detail in Chapter 21 and the debug interface is described in Sec tion 21 4 Chapter 1 Introduction FE310 G003 Manual SiFive Inc Page 12 ...

Страница 15: ...egrated Memory ITIM Instruction Tightly Integrated Memory JTAG Joint Test Action Group LIM Loosely Integrated Memory Used to describe memory space delivered in a SiFive Core Complex but not tightly integrated to a CPU core PMP Physical Memory Protection PLIC Platform Level Interrupt Controller The global interrupt controller in a RISC V system TileLink A free and open interconnect standard origina...

Страница 16: ... are ignored and reads should ignore the value returned WLRL Write Legal Read Legal field A register field that should only be written with legal values and that only returns legal value if last written with a legal value WPRI Writes Preserve Reads Ignore field A register field that might contain unknown information Reads should ignore the value returned but writes to the whole register should pre...

Страница 17: ...es The E31 supports the following modes Machine Mode User Mode 3 1 Instruction Memory System The instruction memory system consists of a dedicated 16 KiB 2 way set associative instruction cache The access latency of all blocks in the instruction memory system is one clock cycle The instruction cache is not kept coherent with the rest of the platform memory system Writes to instruction memory must ...

Страница 18: ...ted ITIM space is automatically returned to the instruction cache For determinism software must clear the contents of ITIM after allocating it It is unpredictable whether ITIM contents are preserved between deallocation and allocation 3 2 Instruction Fetch Unit The E31 instruction fetch unit contains branch prediction hardware to improve performance of the processor core The branch predictor compr...

Страница 19: ...age Correctly predicted branches and jumps incur no penalty whereas mispredicted branches and jumps incur a three cycle penalty Most CSR writes result in a pipeline flush with a five cycle penalty 3 4 Data Memory System The E31 data memory system consists of a DTIM The access latency from a core to its own DTIM is two clock cycles for full words and three clock cycles for smaller quantities Misali...

Страница 20: ...Functional Description The E31 includes a PMP unit which can be used to restrict access to memory and isolate processes from each other The E31 PMP unit has 8 regions and a minimum granularity of 4 bytes Overlapping regions are permitted The E31 PMP unit implements the architecturally defined pmpcfgX CSRs pmpcfg0 and pmpcfg1 supporting 8 regions pmpcfg2 and pmpcfg3 are implemented but hardwired to...

Страница 21: ...orresponding counter and the mhpmcounter_ih CSR holds the 8 most significant bits The event selectors are partitioned into two fields as shown in Table 3 the lower 8 bits select an event class and the upper bits form a mask of events in that class The counter increments if the event corresponding to any set mask bit occurs For example if mhpmevent3 is set to 0x4200 then mhpmcounter3 will increment...

Страница 22: ...erlock 9 Long latency interlock 10 CSR read interlock 11 Instruction cache ITIM busy 12 Data cache DTIM busy 13 Branch direction misprediction 14 Branch jump target misprediction 15 Pipeline flush from CSR write 16 Pipeline flush from other event 17 Integer multiplication interlock Memory System Events mhpeventX 7 0 2 Bits Meaning 8 Instruction cache miss 9 Memory mapped I O access Chapter 3 E31 R...

Страница 23: ...ed 0x0000_3000 0x0000_3FFF RWX A Error Device 0x0000_4000 0x0001_FFFF Reserved None 0x0002_0000 0x0002_1FFF R XC OTP Memory Region 0x0002_2000 0x01FF_FFFF Reserved On Chip Non Volatile Mem ory 0x0200_0000 0x0200_FFFF RW A CLINT 0x0201_0000 0x07FF_FFFF Reserved 0x0800_0000 0x0800_1FFF RWX A E31 ITIM 8 KiB 0x0800_2000 0x0BFF_FFFF Reserved 0x0C00_0000 0x0FFF_FFFF RW A PLIC 0x1000_0000 0x1000_0FFF RW ...

Страница 24: ...001_6000 0x1001_6FFF RW A I2C 0 0x1001_7000 0x1002_2FFF Reserved 0x1002_3000 0x1002_3FFF RW A UART 1 0x1002_4000 0x1002_4FFF RW A SPI 1 0x1002_5000 0x1002_5FFF RW A PWM 1 0x1002_6000 0x1003_3FFF Reserved 0x1003_4000 0x1003_4FFF RW A SPI 2 0x1003_5000 0x1003_5FFF RW A PWM 2 0x1003_6000 0x1FFF_FFFF Reserved 0x2000_0000 0x3FFF_FFFF R XC QSPI 0 Flash 512 MiB 0x4000_0000 0x7FFF_FFFF Reserved Off Chip N...

Страница 25: ...Purpose 00 loops forever waiting for debugger 01 jump directly to 0x2000_0000 memory mapped QSPI0 10 jump directly to 0x0002_0000 OTP 11 jump directly to 0x0002_0000 OTP 5 1 Reset Vector On power on the core s reset vector is 0x1004 Table 6 Reset vector ROM Address Contents 0x1000 The MSEL pin state 0x1004 auipc t0 0 0x1008 lw t1 4 t0 0x100C slli t1 t1 0x3 0x1010 add t0 t0 t1 0x1014 lw t0 252 t0 F...

Страница 26: ...ords from the OTP Instruction fetches from the OTP memory read port are cached in the E31 core s instruction cache The OTP needs to be programmed before use and can only be programmed by code running on the core The OTP bits contain all 0s prior to programming 5 1 2 Quad SPI Flash Controller QSPI The dedicated QSPI flash controller connects to external SPI flash devices that are used for execute i...

Страница 27: ...in the AON block Chapter 12 or the PRCI block Section 6 2 6 1 Clock Generation Overview Figure 2 FE310 G003 clock generation scheme Figure 2 shows an overview of the FE310 G003 clock generation scheme Most digital clocks on the chip are divided down from a central high frequency clock hfclk produced from either the PLL or an on chip trimmable oscillator The PLL can be driven from either the on chi...

Страница 28: ...ON block units Table 8 shows the memory map for the PRCI on the FE310 G003 Offset Name Description 0x00 hfrosccfg Ring Oscillator Configuration and Status 0x04 hfxosccfg Crystal Oscillator Configuration and Status 0x08 pllcfg PLL Configuration and Status 0x0C plloutdiv PLL Final Divide Configuration 0xF0 procmoncfg Process Monitor Configuration and Status 6 3 Internal Trimmable Programmable 72 MHz...

Страница 29: ...divider can be changed at any time The HFROSC is the default clock source used for the system core at reset After a reset the hfrosctrim value is reset to 16 the middle of the adjustable range and the divider is reset to divide by 5 hfroscdiv 4 which gives a nominal 13 8 MHz 50 output frequency The value of hfrosctrim that most closely achieves an 72 MHz clock output at nominal condi tions 1 8 V a...

Страница 30: ... Description 29 0 Reserved 30 hfxoscen RW 0x1 Crystal Oscillator Enable 31 hfxoscrdy RO X Crystal Oscillator Ready The hfxoscen bit turns on the crystal driver and is set on wakeup reset but can be cleared to turn off the crystal driver and reduce power consumption The hfxoscrdy bit indicates if the crystal oscillator output is ready for use The hfxoscen bit must also be turned on to use the HFXOS...

Страница 31: ...llf 2 0 pllq 1 0 The frequency constraints must be observed between each stage for correct operation Figure 3 Controlling the FE310 G003 PLL output frequency The pllr 1 0 field encodes the reference clock divide ratio as a 2 bit binary value where the value is one less than the divide ratio i e 00 1 11 4 The frequency of the output of the refer ence divider refr must lie between 6 12 MHz The pllf ...

Страница 32: ...drive the final hfclk with the PLL output bypassed or otherwise When pllsel is clear the hfroscclk directly drives hfclk The pllsel bit is clear on wakeup reset The pllcfg register is reset to bypass and power off the PLL pllbypass 1 input driven from external HFXOSC oscillator pllrefsel 1 PLL not driving system clock pllsel 0 and the PLL ratios are set to R 2 F 64 and Q 8 pllr 01 pllf 011111 pllq...

Страница 33: ...utdivby1 1 6 7 Internal Programmable Low Frequency Ring Oscillator LFROSC A second programmable ring oscillator LFROSC is used to provide an internal low frequency 32 kHz clock source The LFROSC can generate frequencies in the range 1 5 230 kHz 45 The lfrosccfg register lives in the AON block as shown in Table 35 At power on reset the LFROSC resets to selecting the middle tap lfrosctrim 16 and 5 l...

Страница 34: ... the FE310 G003 and their initial reset conditions At external reset the AON domain lfclk is clocked by either the LFROSC or psdlfaltclk as selected by psdlfaltclksel At wakeup reset the MOFF domain hfclk is clocked by the HFROSC Table 15 FE310 G003 Clock Sources Frequency Name Reset Source Reset Min Max Notes AON Domain LFROSC lfroscrst 32 kHz 1 5 kHz 230 kHz 45 psdlfaltclk 0 kHz 500 kHz When sel...

Страница 35: ...Table 15 FE310 G003 Clock Sources PLL hfclkrst OFF 0 375 MHz 384 MHz JTAG TCK OFF 0 MHz 16 MHz Chapter 6 Clock Generation FE310 G003 Manual SiFive Inc Page 33 ...

Страница 36: ...ssor pipeline All state is preserved in the system The processor will resume in Run mode when there is a local interrupt pending or when the PLIC sends an interrupt notification The processor may also exit wait mode for other events and software must check system status when exiting wait mode to determine the correct course of action 7 3 Sleep Mode Sleep mode is entered by writing to a memory mapp...

Страница 37: ...tialize the core and can interrogate the PMU pmucause register to determine the cause of reset and can recover pre sleep state from the backup registers The processor always initially runs from the HFROSC at the default setting and must reconfigure clocks to run from an alternate clock source HFXOSC or PLL or at a different setting on the HFROSC Because the FE310 G003 has no internal power regulat...

Страница 38: ...esses are required to determine the cause of the interrupt Software and timer interrupts are local interrupts generated by the Core Local Interruptor CLINT The FE310 G003 contains no other local interrupt sources Global interrupts by contrast are routed through a Platform Level Interrupt Controller PLIC which can direct interrupts to any hart in the system via the external interrupt Decoupling glo...

Страница 39: ...is copied into mcause MPIE and then mstatus MIE is cleared effectively disabling interrupts The privilege mode prior to the interrupt is encoded in mstatus MPP The current pc is copied into the mepc register and then pc is set to the value specified by mtvec as defined by the mtvec MODE described in Table 18 At this point control is handed over to software in the interrupt handler with interrupts ...

Страница 40: ...tains fields unrelated to interrupts For the full description of mstatus please consult the The RISC V Instruction Set Manual Volume II Privileged Architecture Version 1 10 Table 16 FE310 G003 mstatus Register partial Machine Status Register CSR mstatus Bits Field Name Attr Description 2 0 Reserved WPRI 3 MIE RW Machine Interrupt Enable 6 4 Reserved WPRI 7 MPIE RW Machine Previous Interrupt Enable...

Страница 41: ... Table 18 for a description of the mtvec MODE field See Table 22 for the FE310 G003 interrupt exception code values Mode Direct When operating in direct mode all synchronous exceptions and asynchronous interrupts trap to the mtvec BASE address Inside the trap handler software must read the mcause register to determine what triggered the trap Mode Vectored While operating in vectored mode interrupt...

Страница 42: ...2 0 Reserved WPRI 3 MSIE RW Machine Software Interrupt Enable 6 4 Reserved WPRI 7 MTIE RW Machine Timer Interrupt Enable 10 8 Reserved WPRI 11 MEIE RW Machine External Interrupt Enable 31 12 Reserved WPRI 8 3 4 Machine Interrupt Pending mip The machine interrupt pending mip register indicates which interrupts are currently pending The mip register is described in Table 20 Table 20 mip Register Mac...

Страница 43: ...et to 0x8000_0007 mcause is also used to indicate the cause of synchronous exceptions in which case the most significant bit of mcause is set to 0 See Table 21 for more details about the mcause register Refer to Table 22 for a list of synchro nous exception codes Table 21 mcause Register Machine Cause Register CSR mcause Bits Field Name Attr Description 9 0 Exception Code WLRL A code identifying t...

Страница 44: ...nvironment call from M mode 0 12 Reserved 8 4 Interrupt Priorities Individual priorities of global interrupts are determined by the PLIC as discussed in Chapter 10 FE310 G003 interrupts are prioritized as follows in decreasing order of priority Machine external interrupts Machine software interrupts Machine timer interrupts 8 5 Interrupt Latency Interrupt latency for the FE310 G003 is 4 cycles as ...

Страница 45: ...ed by coreClk This means that the total latency in cycles for a global interrupt is 4 3 This is a best case cycle count and assumes the handler is cached or located in ITIM It does not take into account additional latency from a peripheral source Chapter 8 Interrupts FE310 G003 Manual SiFive Inc Page 43 ...

Страница 46: ...ed Architecture Version 1 10 9 1 CLINT Memory Map Table 23 shows the memory map for CLINT on SiFive FE310 G003 Table 23 CLINT Register Map Address Width Attr Description Notes 0x2000000 4B RW msip for hart 0 MSIP Registers 1 bit wide 0x2004008 0x200bff7 Reserved 0x2004000 8B RW mtimecmp for hart 0 MTIMECMP Registers 0x2004008 0x200bff7 Reserved 0x200bff8 8B RW mtime Timer Register 0x200c000 Reserv...

Страница 47: ... interprocessor communication in multi hart systems as harts may write each other s msip bits to effect interprocessor interrupts 9 3 Timer Registers mtime is a 64 bit read write register that contains the number of cycles counted from the rtcclk input described in Chapter 12 A timer interrupt is pending whenever mtime is greater than or equal to the value in the mtimecmp register The timer interr...

Страница 48: ... G003 PLIC control registers is shown in Table 24 The PLIC memory map has been designed to only require naturally aligned 32 bit memory accesses Table 24 SiFive PLIC Register Map Only naturally aligned 32 bit memory accesses are required PLIC Register Map Address Width Attr Description Notes 0x0C00_0000 Reserved 0x0C00_0004 4B RW source 1 priority 0x0C00_00D0 4B RW source 52 priority See Section 1...

Страница 49: ...W Hart 0 M Mode claim com plete See Section 10 7 for more information 0x0C20_0008 Reserved 0x1000_0000 End of PLIC Memory Map 10 2 Interrupt Sources The FE310 G003 has 52 interrupt sources These are driven by various on chip devices as listed in Table 25 These signals are positive level triggered In the PLIC as specified in The RISC V Instruction Set Manual Volume II Privileged Architec ture Versi...

Страница 50: ...rupts with the lowest ID have the highest effective priority See Table 26 for the detailed register description Table 26 PLIC Interrupt Priority Registers PLIC Interrupt Priority Register priority Base Address 0x0C00_0000 4 Interrupt ID Bits Field Name Attr Rst Description 2 0 Priority RW X Sets the priority for a given global inter rupt 31 3 Reserved RO 0 10 4 Interrupt Pending Bits The current s...

Страница 51: ...errupt Pending Register 2 PLIC Interrupt Pending Register 2 pending2 Base Address 0x0C00_1004 Bits Field Name Attr Rst Description 0 Interrupt 32 Pend ing RO 0 Pending bit for global interrupt 32 20 Interrupt 52 Pend ing RO 0 Pending bit for global interrupt 52 31 21 Reserved WIRI X 10 5 Interrupt Enables Each global interrupt can be enabled by setting the corresponding bit in the enables register...

Страница 52: ...enable2 for Hart 0 M Mode Base Address 0x0C00_2004 Bits Field Name Attr Rst Description 0 Interrupt 32 Enable RW X Enable bit for global interrupt 32 20 Interrupt 52 Enable RW X Enable bit for global interrupt 52 31 21 Reserved RO 0 10 6 Priority Thresholds The FE310 G003 supports setting of an interrupt priority threshold via the threshold register The threshold is a WARL field where the FE310 G0...

Страница 53: ... A FE310 G003 hart can perform a claim at any time even if the MEIP bit in its mip Table 20 register is not set The claim operation is not affected by the setting of the priority threshold register 10 8 Interrupt Completion A FE310 G003 hart signals it has completed executing an interrupt handler by writing the inter rupt ID it received from the claim to the claim complete register Table 32 The PL...

Страница 54: ...ion of the interrupt id written 10 9 Error Device The error device is a TileLink slave that responds to all requests with a TileLink error It has no registers The entire memory range discards writes and returns zeros on read Both operation acknowledgments carry an error indication The error device serves a dual role Internally it is used as a landing pad for illegal off chip requests However it al...

Страница 55: ...s clock is running Programmed I O reads and writes are sequenced entirely by software 11 1 Memory Map The memory map for the OTP control registers is shown in Table 33 The control register mem ory map has been designed to only require naturally aligned 32 bit memory accesses The OTP controller also contains a read sequencer which exposes the OTP s contents as a read exe cute only memory mapped dev...

Страница 56: ... return 0 immedi ately The otp_lock should be acquired before writing to any other control register Software can attempt to acquire the lock by storing 1 to otp_lock If a memory mapped read is in progress the lock will not be acquired and will retain the value 0 Software can check if the lock was suc cessfully acquired by loading otp_lock and checking that it has the value 1 After a programmed I O...

Страница 57: ...cles is set by a programma ble clock divider The divider is controlled by the otp_rsctrl register the layout of which is shown in Table 34 The number of clock cycles in each phase is given by and the width of each phase may be optionally scaled by 3 That is the number of controller clock cycles in the address setup phase is given by the expression the number of clock cycles in the read pulse phase...

Страница 58: ...ead successfully 2 SET the programming voltages by writing the following values otp_mrr 0x4 otp_mpp 0x0 otp_vppen 0x0 3 WAIT 20 us for the programming voltages to stabilize 4 ADDRESS the memory by setting otp_a 5 WRITE one bit at a time a Set only the bit you want to write high in otp_d b Bring otp_ck HIGH for 50 us c Bring otp_ck LOW Note that this means only one bit of otp_d should be high at an...

Страница 59: ...ain that includes real time counter a watchdog timer backup registers low frequency clocking and reset and power management circuitry for the rest of the system Figure 5 shows an overview of the AON block Figure 5 FE310 G003 Always On Domain FE310 G003 Manual SiFive Inc Page 57 ...

Страница 60: ...g unit reset ndreset or expiration of the watchdog timer wdogrst These sources provide a short initial reset pulse frst which is extended by a reset stretcher to provide the LFROSC reset signal lfroscrst and a longer stretched internal reset srst The lfroscrst signal is used to initialize the ring oscillator in the LFROSC This oscillator pro vides lfclk which is used to clock the AON lfclk is also...

Страница 61: ...he watchdog timer can be used to provide a watchdog reset function or a periodic timer inter rupt The watchdog is described in detail in Chapter 13 12 8 Real Time Clock RTC The real time clock maintains time for the system and can also be used to generate interrupts for timed wakeup from sleep mode or timer interrupts during normal operation The Real Time Clock is described in detail in Chapter 15...

Страница 62: ...cillator Configuration and Status 0x080 backup_0 Backup Register 0 0x084 backup_1 Backup Register 1 0x088 backup_2 Backup Register 2 0x08C backup_3 Backup Register 3 0x090 backup_4 Backup Register 4 0x094 backup_5 Backup Register 5 0x098 backup_6 Backup Register 6 0x09C backup_7 Backup Register 7 0x0A0 backup_8 Backup Register 8 0x0A4 backup_9 Backup Register 9 0x0A8 backup_10 Backup Register 10 0...

Страница 63: ...up program instruction 7 0x120 pmusleepi0 Sleep program instruction 0 0x124 pmusleepi1 Sleep program instruction 1 0x128 pmusleepi2 Sleep program instruction 2 0x12C pmusleepi3 Sleep program instruction 3 0x130 pmusleepi4 Sleep program instruction 4 0x134 pmusleepi5 Sleep program instruction 5 0x138 pmusleepi6 Sleep program instruction 6 0x13C pmusleepi7 Sleep program instruction 7 0x140 pmuie PMU...

Страница 64: ...trigger a full power on reset To prevent errant code from resetting the counter the WDT registers can only be updated by presenting a WDT key sequence w dogcm p w dogcf g w dogcm pi p w dogcl k aonrst w dogcount w dogs w dogscal e Wdog TileLink w dogf eed reset w dogrst aonrst en w dogcl k w dogkey corerst Synch w dogzerocm p w dogrst en w dogenal w ays w dogencoreaw ake Figure 6 Watchdog Timer 13...

Страница 65: ...tion 3 0 wdogscale RW X Counter scale value 7 4 Reserved 8 wdogrsten RW 0x0 Controls whether the comparator output can set the wdogrst bit and hence cause a full reset 9 wdogzerocmp RW X Reset counter to zero after match 11 10 Reserved 12 wdogenalways RW 0x0 Enable Always run continuously 13 wdogcoreawake RW 0x0 Increment the watchdog counter if the processor is not asleep 27 14 Reserved 28 wdogip...

Страница 66: ...are value in wdogcmp This feature can be used to implement periodic counter interrupts where the period is independent of interrupt service time The wdogrsten bit controls whether the comparator output can set the wdogrst bit and hence cause a full reset The wdogip0 interrupt pending bit can be read or written 13 4 Watchdog Compare Register wdogcmp wdogcmp0 Comparator 0 wdogcmp0 Register Offset 0x...

Страница 67: ...3 7 Watchdog Configuration The WDT provides watchdog intervals of up to over 18 hours 65 535 seconds 13 8 Watchdog Resets If the watchdog is not fed before the wdogcount register exceeds the compare register zero while the WDT is enabled a reset pulse is sent to the reset circuitry and the chip will go through a complete power on sequence The WDT will be initalized after a full reset with the wdog...

Страница 68: ...wer management unit PMU is implemented within the AON domain and sequences the system s power supplies and reset signals during power on reset and when tran sitioning the mostly off MOFF block into and out of sleep mode FE310 G003 Manual SiFive Inc Page 66 ...

Страница 69: ... reset wakeup events and sleep requests When the MOFF block is powered off the PMU monitors AON signals to initiate the wakeup sequence When the MOFF block is powered on the PMU awaits sleep requests from the MOFF block which initiate the sleep sequence The PMU is based around a simple pro grammable microcode sequencer that steps through short programs to sequence output signals that control the p...

Страница 70: ...pi5 Sleep program instruction 5 0x138 pmusleepi6 Sleep program instruction 6 0x13C pmusleepi7 Sleep program instruction 7 0x140 pmuie PMU Interrupt Enables 0x144 pmucause PMU Wakeup Cause 0x148 pmusleep Initiate PMU Sleep Sequence 0x14C pmukey PMU Key Reads as 1 when PMU is unlocked 14 3 PMU Key Register pmukey The pmukey register has one bit of state To prevent spurious sleep or PMU program modif...

Страница 71: ...synchronously set to 1 by aonrst PMU Instruction Format pmu sleep wakeup iX Register Offset 0x100 Bits Field Name Attr Rst Description 3 0 delay RW X delay multiplier 4 pmu_out_0_en RW X Drive PMU Output En 0 High 5 pmu_out_1_en RW X Drive PMU Output En 1 High 7 corerst RW X Core Reset 8 hfclkrst RW X High Frequency Clock Reset 9 isolate RW X Isolate MOFF to AON Power Domains At power on reset the...

Страница 72: ... deglitch circuit that requires the dwakeup signal remain asserted for two AON clock edges before being accepted The conditioning circuit also resynchronizes the dwakeup signal to the AON lfclk 14 7 PMU Interrupt Enables pmuie and Wakeup Cause pmucause The pmuie register indicates which events can wake the MOFF block from sleep The dwakeup bit indicates that a logic 0 on the dwakeup_n pin can rous...

Страница 73: ... triggered the wakeup Table 45 lists the values the resetcause field may take The value in resetcause persists until the next reset pmucause PMU Wakeup Cause pmucause Register Offset 0x144 Bits Field Name Attr Rst Description 31 0 pmucause RO X PMU Wakeup Cause Table 44 Wakeup cause values Index Meaning 0 Reset 1 RTC Wakup rtc 2 Digitial input wakeup dwakeup Table 45 Reset cause values Index Meani...

Страница 74: ... cen rt cscal e Figure 8 Real Time Clock 15 1 RTC Count Registers rtccounthi rtccountlo The real time counter is based around the rtccounthi rtccountlo register pair which incre ment at the low frequency clock rate when the RTC is enabled The rtccountlo register holds the low 32 bits of the RTC while rtccounthi holds the upper 16 bits of the RTC value The total 48 bit counter width ensures there w...

Страница 75: ...pt 0 Pending 31 29 Reserved The rtcenalways bit controls whether the RTC is enabled and is reset on AON reset The 4 bit rtcscale field scales the real time counter value before feeding to the real time inter rupt comparator The value in rtcscale is the bit position within the rtccountlo rtccounthi register pair of the start of a 32 bit field rtcs A value of 0 in rtcscale indicates no scaling and r...

Страница 76: ...lock counter If rtcs is greater than or equal to rtccmp the rtccmpip interrupt pending bit is set The rtccmpip interrupt pending bit is read only The rtccmpip bit can be cleared down by writing a value to rtccmp that is greater than rtcs rtccmp0 Comparator 0 rtccmp0 Register Offset 0x60 Bits Field Name Attr Rst Description 31 0 rtccmp0 RW X Comparator 0 Table 49 rtccmp0 Comparator 0 Chapter 15 Rea...

Страница 77: ...is responsible for low level configuration of actual GPIO pads on the device direction pull up enable and drive value as well as selecting between various sources of the controls for these signals The GPIO controller allows separate configuration of each of ngpio GPIO bits Figure 9 shows the control structure for each pin Atomic operations such as toggles are natively possible with the RISC V A ex...

Страница 78: ...Figure 9 Structure of a single GPIO Pin with Control Registers This structure is repeated for each pin Chapter 16 General Purpose Input Output Controller FE310 G003 Manual SiFive Inc Page 76 ...

Страница 79: ...ut enable 0x0C output_val Output value 0x10 pue Internal pull up enable 0x14 ds Pin drive strength 0x18 rise_ie Rise interrupt enable 0x1C rise_ip Rise interrupt pending 0x20 fall_ie Fall interrupt enable 0x24 fall_ip Fall interrupt pending 0x28 high_ie High interrupt enable 0x2C high_ip High interrupt pending 0x30 low_ie Low interrupt enable 0x34 low_ip Low interrupt pending 0x38 iof_en I O funct...

Страница 80: ...being sampled by the interrupt logic so the input pulse width must be long enough to be detected by the synchronization logic To enable an interrupt set the corresponding bit in the rise_ie and or fall_ie to 1 If the cor responding bit in rise_ip or fall_ip is set an interrupt pin is raised Once the interrupt is pending it will remain set until a 1 is written to the _ip register at that bit The in...

Страница 81: ...lled by hardware driving the IOF Which functionalities are controlled by the IOF and which are controlled by the software registers are fixed in the hardware on a per IOF basis Those that are not controlled by the hardware continue to be controlled by the software registers If there is no IOFx for a pin configured with IOFx the pin reverts to full software control Table 52 GPIO IOF Mapping GPIO Nu...

Страница 82: ...Table 52 GPIO IOF Mapping GPIO Number IOF0 IOF1 20 PWM1_PWM0 21 PWM1_PWM2 22 PWM1_PWM3 23 UART1_RX Chapter 16 General Purpose Input Output Controller FE310 G003 Manual SiFive Inc Page 80 ...

Страница 83: ...ive FIFO buffers with programmable watermark interrupts 16 Rx oversampling with 2 3 majority voting per bit The UART peripheral does not support hardware flow control or other modem control signals or synchronous serial data transfers 17 2 UART Instances in FE310 G003 FE310 G003 contains two UART instances Their addresses and parameters are shown in Table 53 Table 53 UART Instances Instance Num be...

Страница 84: ...ansmit FIFO if the FIFO is able to accept new entries Reading from txdata returns the current value of the full flag and zero in the data field The full flag indicates whether the transmit FIFO is able to accept new entries when set writes to data are ignored A RISC V amoor w instruction can be used to both read the full status and attempt to enqueue data with a non zero return value indicating th...

Страница 85: ...channel The txen bit con trols whether the Tx channel is active When cleared transmission of Tx FIFO contents is sup pressed and the txd pin is driven high The nstop field specifies the number of stop bits 0 for one stop bit and 1 for two stop bits The txcnt field specifies the threshold at which the Tx FIFO watermark interrupt triggers The txctrl register is reset to 0 Transmit Control Register t...

Страница 86: ...he read write ie register controls which UART interrupts are enabled ie is reset to 0 The txwm condition becomes raised when the number of entries in the transmit FIFO is strictly less than the count specified by the txcnt field of the txctrl register The pending bit is cleared when sufficient entries have been enqueued to exceed the watermark The rxwm condition becomes raised when the number of e...

Страница 87: ...ud output out of reset given the expected frequency of tlclk Table 61 shows divisors for some common core clock rates and commonly used baud rates Note that the table shows the divide ratios which are one greater than the value stored in the div register Table 61 Common baud rates MIDI 31250 DMX 250000 and required divide values to achieve them with given bus clock frequencies The divide val ues a...

Страница 88: ... 115200 3333 115211 0 01 384 250000 1536 250000 0 384 1843200 208 1846153 0 16 The receive channel is sampled at 16 the baud rate and a majority vote over 3 neighboring bits is used to determine the received value For this reason the divisor must be 16 for a receive channel Baud Rate Divisor Register div Register Offset 0x18 Bits Field Name Attr Rst Description 15 0 div RW X Baud rate divisor div_...

Страница 89: ...ws memory mapped reads under the assumption that the input clock rate is less than 100 MHz and the external SPI flash device supports the common Win bond Numonyx serial read 0x03 command Sequential accesses are automatically combined into one long read command for higher performance The fctrl register controls switching between the memory mapped and programmed I O modes if applicable While in prog...

Страница 90: ...sor 0x04 sckmode Serial clock mode 0x08 Reserved 0x0C Reserved 0x10 csid Chip select ID 0x14 csdef Chip select default 0x18 csmode Chip select mode 0x1C Reserved 0x20 Reserved 0x24 Reserved 0x28 delay0 Delay control 0 0x2C delay1 Delay control 1 0x30 Reserved 0x34 Reserved 0x38 Reserved 0x3C Reserved 0x40 fmt Frame format 0x44 Reserved Table 64 Register offsets within the SPI memory map Registers ...

Страница 91: ...sor used for generating the serial clock SCK The relationship between the input clock and SCK is given by the following for mula The input clock is the bus clock tlclk The reset value of the div field is 0x3 Serial Clock Divisor Register sckdiv Register Offset 0x0 Bits Field Name Attr Rst Description 11 0 div RW 0x3 Divisor for serial clock div_width bits wide 31 12 Reserved Table 64 Register offs...

Страница 92: ...f SCK is logical 1 Value Description 0 Data is sampled on the leading edge of SCK and shifted on the trailing edge of SCK 1 Data is shifted on the leading edge of SCK and sampled on the trailing edge of SCK 18 6 Chip Select ID Register csid The csid is a bit register that encodes the index of the CS pin to be toggled by hardware chip select control The reset value is 0x0 Chip Select ID Register cs...

Страница 93: ...mode register defines the hardware chip select behavior as described in Table 71 The reset value is 0x0 AUTO In HOLD mode the CS pin is deasserted only when one of the fol lowing conditions occur A different value is written to csmode or csid A write to csdef changes the state of the selected pin Direct mapped flash mode is enabled Chip Select Mode Register csmode Register Offset 0x18 Bits Field N...

Страница 94: ... and the deassertion of CS When sckmode pha 1 an additional half period delay is implicit The reset value is 0x1 The intercs field specifies the minimum CS inactive time between deassertion and assertion The reset value is 0x1 The interxfr field specifies the delay between two consecutive frames without deasserting CS This is applicable only when sckmode is HOLD or OFF The reset value is 0x0 Delay...

Страница 95: ...orresponding to proto single dir Tx endian MSB and len 8 For non flash enabled SPI controllers the reset value is 0x0008_0000 corresponding to proto single dir Rx endian MSB and len 8 Frame Format Register fmt Register Offset 0x40 Bits Field Name Attr Rst Description 1 0 proto RW 0x0 SPI protocol 2 endian RW 0x0 SPI endianness 3 dir RW X SPI I O direction This is reset to 1 for flash enabled SPI c...

Страница 96: ...value contained in the data field For fmt len 8 values should be left aligned when fmt endian MSB and right aligned when fmt endian LSB The full flag indicates whether the transmit FIFO is ready to accept new entries when set writes to txdata are ignored The data field returns 0x0 when read Transmit Data Register txdata Register Offset 0x48 Bits Field Name Attr Rst Description 7 0 data RW 0x0 Tran...

Страница 97: ...smit Watermark Register txmark The txmark register specifies the threshold at which the Tx FIFO watermark interrupt triggers The reset value is 1 for flash enabled SPI controllers and 0 for non flash enabled SPI con trollers Transmit Watermark Register txmark Register Offset 0x50 Bits Field Name Attr Rst Description 2 0 txmark RW X Transmit watermark The reset value is 1 for flash enabled controll...

Страница 98: ...tion becomes raised when the number of entries in the receive FIFO is strictly greater than the count specified by the rxmark register The pending bit is cleared when suffi cient entries have been dequeued to fall below the watermark See Table 84 SPI Interrupt Enable Register ie Register Offset 0x70 Bits Field Name Attr Rst Description 0 txwm RW 0x0 Transmit watermark enable 1 rxwm RW 0x0 Receive ...

Страница 99: ...ect mapped memory region is accessed while in SPI flash mode An instruction consists of a command byte followed by a variable number of address bytes dummy cycles padding and data bytes Table 86 describes the function and reset value of each field SPI Flash Instruction Format Register ffmt Register Offset 0x64 Bits Field Name Attr Rst Description 0 cmd_en RW 0x1 Enable sending of command 3 1 addr_...

Страница 100: ...tes 15 14 Reserved 23 16 cmd_code RW 0x3 Value of command byte 31 24 pad_code RW 0x0 First 8 bits to transmit during dummy cycles Table 86 SPI Flash Instruction Format Register Chapter 18 Serial Peripheral Interface SPI FE310 G003 Manual SiFive Inc Page 98 ...

Страница 101: ... types of waveforms on output pins pwm gpio and can also be used to generate several forms of internal timer interrupt The comparator results are captured in the pwmcmp ip flops and then fed to the PLIC as potential interrupt sources The pwmcmp ip outputs are further processed by an output ganging stage before being fed to the GPIOs PWM instances can support comparator precisions cmpwidth up to 16...

Страница 102: ...esses and parameters are shown in Table 87 Table 87 PWM Instances Instance Number Address ncmp cmpwidth 0 0x10015000 4 8 1 0x10025000 4 16 2 0x10035000 4 16 19 3 PWM Memory Map The memory map for the PWM peripheral is shown in Table 88 Chapter 19 Pulse Width Modulator PWM FE310 G003 Manual SiFive Inc Page 100 ...

Страница 103: ... counter is held in pwmcount 30 0 and bit 31 of pwmcount returns a zero when read When used for PWM generation the counter is normally incremented at a fixed rate then reset to zero at the end of every PWM cycle The PWM counter is either reset when the scaled counter pwms reaches the value in pwmcmp0 or is simply allowed to wrap around to zero The counter can also be used in one shot mode where it...

Страница 104: ...lways run continuously 13 pwmenoneshot RW 0x0 PWM enable one shot run one cycle 15 14 Reserved 16 pwmcmp0center RW X PWM0 Compare Center 17 pwmcmp1center RW X PWM1 Compare Center 18 pwmcmp2center RW X PWM2 Compare Center 19 pwmcmp3center RW X PWM3 Compare Center 23 20 Reserved 24 pwmcmp0gang RW X PWM0 PWM1 Compare Gang 25 pwmcmp1gang RW X PWM1 PWM2 Compare Gang 26 pwmcmp2gang RW X PWM2 PWM3 Compar...

Страница 105: ...wmscale is the bit position within the pwmcount register of the start of a cmpwidth bit pwms field A value of 0 in pwmscale indicates no scaling and pwms would then be equal to the low cmpwidth bits of pwmcount The maximum value of 15 in pwmscale corre sponds to dividing the clock rate by 215 so for an input bus clock of 16 MHz the LSB of pwms will increment at 488 3 Hz The pwmzerocmp bit if set c...

Страница 106: ...ion 15 0 pwmcmp1 RW X PWM 1 Compare Value 31 16 Reserved PWM 2 Compare Register pwmcmp2 Register Offset 0x28 Bits Field Name Attr Rst Description 15 0 pwmcmp2 RW X PWM 2 Compare Value 31 16 Reserved PWM 3 Compare Register pwmcmp3 Register Offset 0x2C Table 91 Scaled PWM Count Register Table 92 PWM 0 Compare Register Table 93 PWM 1 Compare Register Table 94 PWM 2 Compare Register Table 95 PWM 3 Com...

Страница 107: ... in pwmcfg can be set to capture any high output of a PWM comparator in a sticky bit pwmcmp ip for comparator and prevent the output falling again within the same PWM cycle The pwmcmp ip bits are only allowed to change at the start of the next PWM cycle Note The pwmcmp0ip bit will only be high for one cycle when pwmdeglitch and pwmzerocmp are set where pwmcmp0 is used to define the PWM cycle but c...

Страница 108: ...an be optionally and individually inverted thereby creating left aligned PWM waveforms high at beginning of cycle 19 10 Generating Center Aligned Phase Correct PWM Waveforms The simple PWM waveforms in Figure 11 shift the phase of the waveform along with the duty cycle A per comparator pwmcmp center bit in pwmcfg allows a single PWM comparator to generate a center aligned symmetric duty cycle as s...

Страница 109: ... are shown for a 3 bit PWM precision The signals can be inverted at the GPIOs to generate opposite phase waveforms When a comparator is operating in center mode the deglitch circuit allows one 0 to 1 transition during the first half of the cycle and one 1 to 0 transition during the second half of the cycle Table 96 Illustration of how count value is inverted before presentation to comparator when ...

Страница 110: ...unter will run for one PWM cycle then once a reset condition occurs the pwmenoneshot bit is reset in hardware to prevent a second cycle 19 13 PWM Interrupts The PWM can be configured to provide periodic counter interrupts by enabling auto zeroing of the count register when a comparator 0 fires pwmzerocmp 1 The pwmsticky bit should also be set to ensure interrupts are not forgotten while waiting to...

Страница 111: ... C Master Core Download the original documentation at https opencores org project i2c All I C control register addresses are 4 byte aligned 20 1 I C Instance in FE310 G003 FE310 G003 contains one I C instance Its address is shown in Table 97 Table 97 I C Instance Instance Number Address 0 0x10016000 FE310 G003 Manual SiFive Inc Page 109 ...

Страница 112: ...le 98 Debug Control and Status Registers CSR Name Description Allowed Access Modes tselect Trace and debug register select D M tdata1 First field of selected TDR D M tdata2 Second field of selected TDR D M tdata3 Third field of selected TDR D M dcsr Debug control and status register D dpc Debug PC D dscratch Debug scratch register D The dcsr dpc and dscratch registers are only accessible in debug ...

Страница 113: ... hold indices of unimplemented TDRs Even if index can hold a TDR index it does not guarantee the TDR exists The type field of tdata1 must be inspected to determine whether the TDR exists 21 1 2 Trace and Debug Data Registers tdata1 3 The tdata1 3 registers are XLEN bit read write registers selected from a larger underlying bank of TDR registers by the tselect register Table 100 tdata1 CSR Trace an...

Страница 114: ...ives information about debug capabilities and status Its detailed functionality is described in The RISC V Debug Specification 0 13 21 1 4 Debug PC dpc When entering debug mode the current PC is copied here When leaving debug mode execu tion resumes at this PC 21 1 5 Debug Scratch dscratch This register is generally reserved for use by Debug ROM in order to save registers needed by the code in Deb...

Страница 115: ...e Attr Rst Description 0 R WARL X Address match on LOAD 1 W WARL X Address match on STORE 2 X WARL X Address match on Instruction FETCH 3 U WARL X Address match on User Mode 4 S WARL X Address match on Supervisor Mode 5 Reserved WPRI X Reserved 6 M WARL X Address match on Machine Mode 10 7 match WARL X Breakpoint Address Match type 11 chain WARL 0 Chain adjacent conditions 17 12 action WARL 0 Brea...

Страница 116: ...ions of implemented bits must be supported The match field is a 4 bit read write WARL field that encodes the type of address range for breakpoint address matching Three different match settings are currently supported exact NAPOT and arbitrary range A single breakpoint register supports both exact address matches and matches with address ranges that are naturally aligned powers of two NAPOT in siz...

Страница 117: ...ter maddress Each breakpoint match address register is an XLEN bit read write register used to hold signifi cant address bits for address matching and also the unary encoded address masking informa tion for NAPOT ranges 21 2 3 Breakpoint Execution Breakpoint traps are taken precisely Implementations that emulate misaligned accesses in soft ware will generate a breakpoint trap when either half of t...

Страница 118: ...a RAM are general purpose RAM and are mapped contiguously in the Core Complex memory space Therefore additional data can be passed in the program buffer and additional instructions can be stored in the debug data RAM Debuggers must not execute program buffer programs that access any debug module memory except defined program buffer and debug data addresses The FE310 G003 does not implement the DMS...

Страница 119: ... Figure 13 The state machine is clocked with TCK All transitions are labelled with the value on TMS except for the arc showing asynchronous reset when TRST 0 Figure 13 JTAG TAPC state machine 21 4 2 Resetting JTAG Logic The JTAG logic must be asynchronously reset by asserting the power on reset signal This dri ves an internal jtag_reset signal Asserting jtag_reset resets both the JTAG DTM and debu...

Страница 120: ...structions The JTAG DTM implements the BYPASS and IDCODE instructions On the FE310 G003 the IDCODE is set to 0x20000913 21 4 5 JTAG Debug Commands The JTAG DEBUG instruction gives access to the SiFive debug module by connecting the debug scan register between jtag_TDI and jtag_TDO The debug scan register includes a 2 bit opcode field a 7 bit debug module address field and a 32 bit data field to al...

Страница 121: ...aterman and K Asanovic Eds The RISC V Instruction Set Manual Volume I User Level ISA Version 2 2 May 2017 Online Available https riscv org specifications 2 The RISC V Instruction Set Manual Volume II Privileged Architecture Version 1 10 May 2017 Online Available https riscv org specifications FE310 G003 Manual SiFive Inc Page 119 ...

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