SiFive’s E31 Core Complex is a high performance implementation of the RISC‑V RV32IMAC
architecture. The SiFive E31 Core Complex is guaranteed to be compatible with all applicable
RISC‑V standards, and this document should be read together with the official RISC‑V user-
level, privileged, and external debug architecture specifications.
A summary of features in the E31 Core Complex can be found in Table 1.
E31 Core Complex Feature Set
Feature
Description
Number of Harts
1 Hart.
E31 Core
1× E31 RISC‑V core.
Local Interrupts
16 Local Interrupt signals per hart which can be connected to
off core complex devices.
PLIC Interrupts
127 Interrupt signals which can be connected to off core
complex devices.
PLIC Priority Levels
The PLIC supports 7 priority levels.
Hardware Breakpoints
4 hardware breakpoints.
Physical Memory Protection
Unit
PMP with 8 x regions and a minimum granularity of 4 bytes.
Table 1:
E31 Core Complex Feature Set
An overview of the SiFive E31 Core Complex is shown in Figure 1. This RISC-V Core IP
includes a 32-bit RISC‑V microcontroller core, memory interfaces including an instruction cache
as well as instruction and data tightly integrated memory, local and global interrupt support,
physical memory protection, a debug unit, outgoing external TileLink platform ports, and an
incoming TileLink master port.
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