Transfer Instructions
54
S7-400 Instruction List
A5E00267845-01
Transfer Instructions
Transferring the contents of ACCU1 to the addressed operand. Note that some instructions are affected by the MCR (see page
LEERER MERKER). The status word is not affected.
In-
Length
Execution Time in
s
In-
struc-
Address
Description
Length
in
Execution Time in
s
struc-
tion
Address
ID
Description
in
Words
CPU 412
CPU 414
CPU 416
CPU 417
T
IB
a
QB
a
PQB
a
Transfer contents of
ACCU1-LL to ...
input byte
output byte
peripheral output byte
2)
1
1)
/2
1
1)
/2
2
0.1/0.125
0.1/0.125
0.125
0.06/0.075
0.06/0.075
0.075
0.04/0.05
0.04/0.05
0.05
0.03/0.042
0.03/0.042
0.042
MB
a
LB
a
bit memory byte
local data byte
1
3)
/2
2
0.1/0.125
0.125
0.06/0.075
0.075
0.04/0.05
0.05
0.03/0.042
0.042
DBB
a
DIB
a
data byte
instance data byte
2
2
0.335
0.335
0.075
0.075
0.05
0.05
0.042
0.042
g [d]
g [AR1,m]
g [AR2,m]
B[AR1,m]
B[AR2,m]
Parameter
Memory-indirect, area internal
Register-ind., area internal (AR1)
Register-ind., area internal (AR2)
Area-crossing (AR1)
Area-crossing (AR2)
Via parameter
2
2
2
2
2
2
0.1+
0.125+
0.125+
0.125+
0.125+
0.125+
0.06+
0.075+
0.075+
0.075+
0.075+
0.075+
0.04+
0.05+
0.05+
0.05+
0.05+
0.05+
0.03+
0.042+
0.042+
0.042+
0.042+
0.042+
+
Plus time required for loading the address of the instruction (see page 20)
1)
With direct instruction addressing; Address area 0 to 127
2)
The following peripheral acknowledgement time must be observed with CPU 414-4H and CPU 417-4H: solo xx
s, redundant xx
s
3)
With direct instruction addressing; Address area 0 to 255