Logic Instructions with Timers and Counters
32
S7-400 Instruction List
A5E00267845-01
Logic Instructions with Timers and Counters, continued
In-
struc-
Length
in
Words
Execution Time in
s
In-
struc-
tion
Address ID
Description
in
Words
Execution Time in
s
CPU 412
CPU 414
CPU 416
CPU 417
O/ON
T
f
T
[e]
C
f
C
[e]
Timer
Timer, memory-indirect addr.
Counter
Counter, memory-indirect addressing
1*/2
2
1*/2
2
0.1/0.125
0.1+
0.1/0.125
0.1+
0.06/0.075
0.06+
0.06/0.075
0.06+
0.04/0.05
0.04+
0.04/0.05
0.04+
0.03/0.042
0.03+
0.03/0.042
0.03+
Timerpara.
Counterpara.
Timer/counter (addressing via parame-
ter)
2
0.1+
0.1+
0.06+
0.06+
0.04+
0.04+
0.03+
0.03+
X/XN
T
f
T
[e]
C
f
C
[e]
EXCLUSIVE OR/EXCLUSIVE OR NOT
Timer
Timer, memory-indirect addr.
Counter
Counter, mem.-indirect addr.
2
2
2
2
0.125
0.1+
0.125
0.1+
0.075
0.06+
0.075
0.06+
0.05
0.04+
0.05
0.04+
0.042
0.03+
0.042
0.03+
Timerpara.
Counterpara.
EXCLUSIVE OR timer/counter (address-
ing via parameter)
2
0.1+
0.1+
0.06+
0.06+
0.04+
0.04+
0.03+
0.03+
Status word for:
O, ON, X, XN
BR
CC1
CC0
OV
OS
OR
STA
RLO
/FC
Instruction evaluates:
–
–
–
–
–
–
–
Yes
Yes
Instruction affects:
–
–
–
–
–
0
Yes
Yes
1
+
Plus time required for loading the address of the instruction (see page 20)
*
)
With direct instruction addressing; address area 0 to 255
