Siemens 7XV5662-0AD00, Инструкция по применению

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7XV5662-0AD00 English
C53000-B1174-C205-1 43
The timeslot 16 is provided for signalling. Frame 0 (Multiframe Alignment Signal) of a
multiframe includes the Y–bit which is set to “1” in the case of Loss of MFAS (Loss of
Multiframe Alignment Signal).
In the subsequent 15 frames (1 to 15) of the multiframe the bits 1 to 8 are set to “1”.
In T1 mode the D4 and ESF frame structure is supported.
The ESF frame structure consists of 24 frames with 193 bits each. The first bit of any frame
is reserved for synchronisation and error indication. The assignment is shown in the
following table. The FAS bits are reserved for synchronisation, and the DL bits form a data
link via which alarms are transmitted. If the synchronisation is lost, the bit pattern
“1111111100000000” is transmitted via the DL bits. A CRC–6 is generated via the user data
and transmitted accordingly. There will be no evaluation or external signalling of the CRC
through the CC–2M.
Bit No. 1 2 3 4 5 6 7 8
0 0 0 0 1 Y 1 1
Multi–frame No. Multi–frame Bit No. FAS DL CRC
1 0 – M –
2 193 – – C1
3 386 – M –
4 579 0 – –
5 772 – M –
6 965 – – C2
7 1158 – M –
8 1351 0 – –
9 1544 – M –
10 1737 – – C3
11 1930 – M –
12 2123 1 – –
13 2316 – M –
14 2509 – – C4
15 2702 – M –
16 2895 0 – –
17 3088 – M –
18 3281 – – C5
19 3474 – M –
20 3667 1 – –
21 3860 – M –