Shuttle XPC SK21G, Руководство пользователя

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DDR Timing Setting
This item allows you to set DRAM timing.
Ø The Choice: Auto or Manual.
Memclock index valux (Whz)
Places an artificial memory clock limit on the system.
Memory is prevented from running faster than this frequency.
Ø The Choice: 100, 133,166 or 200.
CAS# latency (Tc1)
This item defines the timing delay in clock cycles before SDRAM starts
a read command after receiving it.
Ø
The Choice: 2, 2.5 or 3.0.
Min RAS# active time (tRAS)
This precharge time is the number of cycles it takes for DRAM to accu-
mulate its charge before refresh.
Ø The Choice: Auto or 5 ~15 Bus Clocks.
RAS# to CAS# delay (tRCD)
This item defines the timing of the transition from RAS (row address
strobe) to CAS (column address strobe) as both rows and columns are
separately addressed shortly after DRAM is refreshed.
Ø The Choice: Auto or 2 ~7 Bus Clocks.
Row Precharge Time (tRP)
This item defines the numbers of cycles for RAS (row address strobe) to
be allowed to precharge.
Ø
The Choice: Auto or 2 ~7 Bus Clocks.
MTRR mapping mode
This item allows you to set the MTRR mapping mode.
Ø The Choice: Continuous or Discrete.