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CPU to PCI Write Buffer
When this field is Enabled, the writing from CPU to PCI bus is buff-
ered, to compensate for the speed differences between the CPU and
the PCI bus. When Disabled, the writing is are not buffered and the
CPU must wait until the write is complete before starting another
write cycle.
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The Choice: Enabled or Disabled.
PCI Dynamic Bursting
This item allows you to enable/disable the PCI dynamic bursting
function.
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The Choice: Enabled or Disabled.
PCI Master 0 WS Write
When this item enabled, writing to the PCI bus is executed with zero
wait state.
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The Choice: Enabled or Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance
with PCI specification version 2.1.
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The Choice: Enabled or Disabled.
PCI #2 Access #1 Retry
When this item disabled, PCI#2 will not be disconnected until
access finishes (default); On the contrary, PCI#2 will be discon-
nected if max etries are attempted without success.
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The Choice: Enabled or Disabled.
AGP Master 1 WS Write
When this item enabled, writing to the AGP(Accelerated Graphics
Port) is executed with one wait state.
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The Choice: Enabled or Disabled.
AGP Master 1 WS Read
When this item enabled, reading from the AGP (Accelerated Graph-
ics Port) is executed with one wait state.
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The Choice: Enabled or Disabled.
Memory Parity/ECC Check
This item allows you to Enabled/Disabled memory error checking
and correction (ECC). In order for ECC to function, 9-chip (8
memory chips +1 ECC chip) SDRAM modules must be installed on
the mainboard.
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The Choice: Enabled or Disabled.
