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Passive Release
When enabled, the chipset provides a programmable passive release mechanism to meet
the required ISA master latencies.
Delayed Transaction
Since the 2.1 revision of the PCI specification requires much tighter controls on target and
master latency. PCI cycles to or from ISA typically take longer. When enabled, the
chipset provides a programmable delayed completion mechanism to meet the required
target latencies.
AGP Aperture Size (MB)
This item allows the user to set memory-mapped, graphics data structures can reside in
Graphics Aperture.
SDRAM RAS-to-CAS Delay
When SDRAM is refreshed, both rows and columns are address separately. This setup
item allows you to determine the timing of the transition from Row Address Strobe (RAS)
to Column Address Strobe (CAS). The options are
Slow
for 3 and
Fast
for 2
CLKs.
SDRAM RAS Precharge Time
SDRAM must continually be refreshed or it will lose its data. Normally, DRAM is
refreshed entirely as the result of a single request. This option allows you to determine
the number of CPU clocks allocated for Row Address Strobe to accumulate its charge
before the DRAM is refreshed. If insufficient time is allowed, refresh may be incomplete
and data lost. The options are
Slow
for 3 and
Fast
for 2
CLKs.
SDRAM CAS Latency Time
This item defines the CAS Latency timing parameter of the SDRAM expressed in 66MHz
clocks. The options are
2
and
3
CLKs.
Auto Detect DIMM/PCI Clock
Enabling this item allosw system auto detect and close clock signal to empty DIMM/PCI
slot to reduce EMI.
Spread Spectrum Modulated
This item allows the user to enable Spread Spectrum Modulated to reduce the EMI.
CPU Host Clock
This item allows the user to adjust CPU Host Bus Clock from BIOS when JP37 is set to
Auto.
The user may adjust CPU Host Clock from 50 MHz to 83 MHz when 66 MHz based
Pentium II or Celeron processor is used, or from 100 MHz to 112 MHz when 100 MHz
based Pentium II processor is used.
This item will not show up when JP37 is set to Manual.
