Shiratech Solutions Spark-100, Руководство по интеграции, Страница: 23 / 41

23 | Spark-100 HW user manual v1.3
An additional variation is between the SX and SE devices, the difference is the transceivers which are
available on the SX devices. When using a Spark with SE device the following should be done:

The transceivers received lines should be tied to ground .

The transmit lines should be left open .
2.5.2 FPGA IOs
The I/Os available are divided to banks according to the following table:
FPGA bank Number of I/O Voltage supported
Bank 3A 16 1.8V
Bank 3B 32 1.5V, 1.8V, 2.5V, 3.3V
Bank 4A 68 1.5V, 1.8V, 2.5V, 3.3V
Bank 5A 16 1.8V
Bank 5B 7 3.3V
Bank 8A 6 1.8V
Note: All FPGA GPIO which can be differential pairs are routed as pairs to the SMARC connector.
2.5.3 Transceivers
The CycloneV SX family provides 6 transceivers at 3.125 Gigabits per second (Gbps). These transceivers
comply with a wide range of protocols and data rate standards.
On the Spark the transceivers are routed as differential pairs to support high speed applications. The
Spark also provide optional low jitter differential clock using a build in clock generator, with an option to
provide differential clocks.
2.5.4 FPGA configuration
The FPGA can be configured in several ways:
2.5.4.1 Configuration via byte blaster
The Spark has an option for a build in JTAG connector for connecting the byte blaster (for development
boards only), alternatively a byte blaster can be connected via the SMARC interface. For more details
see the paragraph 2.3.8 on JTAG interface.
2.5.4.2 Configuration via Software
The FPGA can be easily configured via Software. The FPGA file should be placed in the FAT part of the SD
used for software. The FPGA file should be in FPP 16(Fast parallel 16 bits), security disable, compression
disable, RBF format, the file should be called fpga.rbf. The FPGA will be programed by the boot software,