Shiratech Solutions Spark-100, Руководство по интеграции, Страница: 14 / 41

14 | Spark-100 HW user manual v1.3
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Compliant with CAN protocol specification 2.0 part A & B.
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Programmable communication rate up to 1 Mbps.
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Holds up to 128 messages.
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Supports 11-bit standard and 29-bit extended identifiers.
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Programmable interrupt scheme.
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Direct access for host processor.
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DMA controller may be used for large transfers.
2.3.5 I2C overview
The Spark-100 uses two I2C buses of the HPS. The HPS offers the following I2C support:
- Maximum clock speed of up to 400 Kbps.
- 7- or 10-bit addressing.
- Mixed read and write combined-format transactions in both 7-bit and 10-bit addressing mode.
- Bulk transmit mode.
- Transmit and receive buffers.
- Handles bit and byte waiting at all bus speeds.
- DMA handshaking interface.
On the SPARK the I2C buses are used as follows:
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I2C0 is expanded to four I2C interfaces in order to meet the SMARC requirements providing
I2C_Cam, I2C_GP, I2C_PM and I2C_LCD buses.
o
The buses can be used for any other application according need.
o
There are pull-up resistors on each bus, so there no need to put pull-up resistors on the
carrier board.
o
The expansion is done using TI TCA9548A (8 channel I2C switch). Buses 0-3 of the device
are connected to the SAMRC connector, the other buses are unused.
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I2C1 is connected to the I2C controlled chips on the SOM and is not available externally. There
are several devices located on I2C1 bus:
o
An I2C I/O expender using TI TCA6416A, for providing additional GPIOs for control and
monitor
o
An E2PROM device Atmel AT24C01C, used for system parameters storage.
o
Control interface for the advanced clock distributor, the CDCM6208 by TI (assembled
only for SOM with Altera SX device) .
o
A Digital Temperature Sensor for monitoring system temperature. The device used is TI
TMP108.