SD-AT100H
– 106 –
53
P1CI
Input
C input. (DVD)
54
P1BI
Input
B input. (DVD)
55
P1AI
Input
A input. (DVD)
56
GNDR
—
GND terminal. (RF)
57
LDP2
Input
APC polarity 2.
58
P2AI
Input
A input. (CD)
59
P2BI
Input
B input. (CD)
60
P2CI
Input
C input. (CD)
61
P2DI
Input
D input. (CD)
62
GNDS
—
GND terminal. (Servo)
63
P2FP
Input
FE+ input. (CD)
64
P2Fn
Input
FE– input. (CD)
IC3301 VHi-1: RF Signal Processor (TA1323F) (2/2)
Terminal Name
Pin No.
Input/Output
Function
Figure 106 BLOCK DIAGRAM OF IC
P1TP
P1TN
LDO1
MDI1
EQF
EQB
VrA
RFDC
TCC1
GND2
NC
NC
Vcc2
DPDB
FEB
TEB
RFS
VccR
RFOp
RFOn
RPP
RPB
RPO
RPZ
NC
VccS
DFTN
FEO
TEO
LVL
VccP
VCKF
P1FN
P1FP
LDP1
P1DI
P1CI
P1BI
P1AI
GNDR
LDP2
P2AI
P2BI
P2CI
P2DI
GNDS
P2FP
P2FN
GND
P2TP
P2TN
LDO2
MDI2
V
rD
V
rfil
V
dd
DPAC
DPBD
DPD1
DPD2
SCB
SCL
SCD
V
RCK
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Time
constant
adjustment
RF Ripple
creation
Output
Amp
T-gain
Adjust
sel-PD
sel-PD
sel-PD
Level
detect
F-gain
Adjust
mode-IC
R-gain
Adjust
3Beam-TE
creation
DPD-TE
creation
FE creation
EQ
APC1
APC2
Vref
BUS
sel-RF
sel-FE
sel-TE
sel-DPD
sel-LVL
mode-TE
F-gain
Adjust
DPDB
TEB
FEB
TEB
TCC1
VrA
tcc1 (BUS)
TE-gain
Adjust
FE-gain
Adjust
DC
FB
Содержание SD-AT100H
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