SPEC No.
LCY-12T09303B
MODEL No.
LS013B4DN02
PAGE
15
6-5) Input Signal Timing Chart
6-5-1 Data update mode (1 line)
Updates data of only one specified line. (M0=”H”
、
M2
＝
”L”)
SCS
SI
M0 M1 M2 DMYDMYDMYDMYDMYAG0 AG1 AG2 AG3 AG4 AG5 AG6 DMY D1 D2 D3 D4
D93 D94 D95 D96
DUMMY DATA(don't care)
SCLK
tsSI
thSI
tsSCS
Data writing period
(96ck)
Data transfer period
(16ck)
Mode selection period
(3ck+5ckDMY)
twSCLKH
twSCLKL
twSCSH
Gate line address period
(7ck+1ckDMY)
thSCS
twSCSL
M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)
When “L”, display mode (maintain memory internal data).
M1: Frame inversion flag.
When “H”, outputs VCOM=”H”, and when “L”, outputs VCOM=”L”.
When EXTMODE=”H”, it can be “H” or “L”.
M2: All clear flag.
Refer to 6-5-4) All Clear Mode to execute clear.
DUMMY DATA: Dummy data. It can be “H” or “L” (“L” is recommended.)
※
Data write period
Data is being stored in 1
st
latch block of binary driver on panel.
※
Data transfer period
Data written in 1
st
latch is being transferred (written) to pixel internal memory circuit.
※
For gate line address setting, refer to 6-6) Input Signal and Display.
※
M1: Frame inversion fl is enaled when EXTMODE=”L”.
※
When SCS becomes
“
L
”
, M0 and M2 are cleared.
