Sharp LC-32DH57E-BK, Руководство по обслуживанию

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LC
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32DH57E-BK/RU-BK/S-BK
5 – 16
2.10.2 Pin Connections and short description
2.11. IC8455 (VHiBR24S64F-1Y)
This IC is a block diagram and description LC-32A47E/RU/V (S59Z4LC32A47E) please see the service manual.
Pin No. Pin Name I/O Pin Function
29-44 IO0-IO7 I/O DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read/program opera-
tions.
The inputs are latched on the rising edge of Write Enable (WE#).
The I/O buffer float to High-Z when the device is deselected or the outputs are disabled.
16 CLE I COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write
Enable (WE#).
17 ALE I ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write
Enable (WE#).
9 CE# I CHIP ENABLE
This input controls the selection of the device. When the device is busy CE# low does not deselect the
memory.
18 WE# I WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge
of WE#.
8 RE# I READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE# which also increments the internal column address counter by one.
19 WP# I WRITE PROTECT
The WP# pin, when Low, provides an Hardware protection against undesired modify (program/erase)
operations.
7 A/B# I READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
37 VCC — SUPPLY VOLTAGE
The VCC supplies the power for all the operations (Read, Write, Erase).
36 VSS — GROUND
1-6, 10-11, 14-15,
20-28, 33-35,
39-40, 45-48 NC — NO CONNECTION