Sharp LC-26SB25E, Руководство по обслуживанию

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2008-03-14
LC-26SB25E/S/RU, LC-32SB25E/S/RU, LC-42SB55E/S/RU
55
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If internal audio DAC is disabled, the MT5337PKR will support 5-bit (10-channel) main audio I2S output interface. Each channel is up to 24-bit
resolution.
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If internal audio DAC is disabled, the MT5337PKR family supports 1-bit (2-channel) aux audio I2S output I/F. Each channel is up to 24-bit resolution.
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Flash Interface
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The MT5337PKR supports two configurations for the flash interface: 1. two serial flashes, or 2. one serial flash and one 8-bit NAND flash (not
OneNAND flash).
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The MT5337PKR supports booting from either one serial flash or NAND flash which can be selected by the settings of strapping at power-on.
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Serial flash interface supports up to 60 MHz clock rate, depending on the spec. of the flash device (currently 20 MHz at maximum)
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NAND flash interface supports 17 Mbytes/sec
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Supports on-the-fly decompression from Serial Flash to DRAM or from NAND Flash to DRAM.
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Peripherals
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Each of the MT5337PKR has two built-in UARTs with Tx and Rx FIFO, one of them has hardware flow control and high speed data transferring.
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The MT5337PKR has five serial interfaces; one is for the tuner, one is the master for general purpose, the other three are the slaves for three HDMI
EDID data.
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Three PWMs
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IR blaster and receiver
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Real-time clock and watchdog controller
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1-port USB2.0/1.1 host supports USB mass storage class devices.
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Supports five-channel servo ADC.
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If NAND flash is not enabled, the MT5337PKR supports xD/SM, MS/MS-PRO, SD/MMC, and SDHC card reader.
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IC Outline
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The MT5337PKR is 465-pin BGA Package
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3.3V/1.1V and 2.5V for DDR1, 1.8V for DDR2
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System Software
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MHEG-5 is supported
1.2. U102 (LP2996MRX PSOP-8)
General Description
The LP2996 linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device contains a high-speed
operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current
and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996 also incorporates a V
SENSE
pin to provide superior
load regulation and a V
REF
output as a reference for the chipset and DIMMs. An additional feature found on the LP2996 is an active low shutdown (SD) pin
that provides Suspend To RAM (STR) functionality. When SD is pulled low the V
TT
output will tri-state providing a high impedance output, but, V
REF
will
remain active. A power savings advantage can be obtained in this mode through lower quiescent current.
Features
·
Source and sink current
·
Low output voltage offset
·
No external resistors required
·
Linear topology
·
Suspend to Ram (STR) functionality
·
Low external component count
·
Thermal Shutdown
·
Available in SO-8, PSOP-8 or LLP-16 packages
Applications
·
DDR-I and DDR-II Termination Voltage
·
SSTL-2 and SSTL-3 Termination
·
HSTL Termination
1.3. U104 (L5985 VFQFPN8)
Description
The L5985 is a step down switching regulator with 2.5A current limited embedded power MOSFET, so it is able to deliver up to 2A DC current to the load
depending on the application condition.
The input voltage can range from 2.9V to 18V, while the output voltage can be set starting from 0.6V to V
IN
. Having a minimum input voltage of 2.9V, the
device is suitable for buses staring from for 3.3V bus.
Requiring a minimum set of external components, the device includes an internal 250KHz switching frequency oscillator that can be externally adjusted up
to 1MHz.
The QFN package with exposed pad allows reducing the R
thJA
down to approximately 60°C/W.
Features
·
2A DC output current
·
2.9V to 18V input voltage
·
Output voltage adjustable from 0.6V
·
250KHz switching frequency, programmable up to 1MHz
·
Internal Soft-start and Inhibit
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Low dropout operation: 100% duty cycle
·
Voltage feed-forward
·
Zero load current operation