Sharp LC-19D1E/S-BK/WH, Руководство по обслуживанию

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LC-19D1E/S-BK/WH
5 – 19
127 PIO0[7] I/O PIO port 0 [7] FERESET
126 PIO0[6] I/O PIO port 0 [6] TSSWITCH
123 PIO0[5] I/O PIO port 0 [5] NOTREADY
122 PIO0[4] I/O PIO port 0 [4] NOTRE-
SETCI
121 PIO0[3] I/O PIO port 0 [3] FLASHWP
120 PIO0[2] I/O PIO port 0 [2] TL
119 PIO0[1] I/O PIO port 0 [1] VCCEN
118 PIO0[0] I/O PIO port 0 [0] CARDVC-
COC
46 PIO1[7] I/O PIO port 1 for card (parallel) FEERROR
45 PIO1[6] I/O PIO port 1 for card (parallel) TSOUTD6
44 PIO1[5] I/O PIO port 1 for card (parallel) TSOUTD5
43 PIO1[4] I/O PIO port 1 for card (parallel) TSOUTD4
41 PIO1[3] I/O PIO port 1 for card (parallel) TSOUTD3
40 PIO1[2] I/O PIO port 1 for card (parallel) TSOUTD2
39 PIO1[1] I/O PIO port 1 for card (parallel) TSOUTD1
38 PIO1[0] I/O PIO port 1 for card (parallel) TSOUTD0
117 PIO2[7] I/O PIO port 2 [7] TL
116 PIO2[6] I/O PIO port 2 [6] TL
115 PIO2[5] I/O PIO port 2 [5] TL
114 PIO2[4] I/O PIO port 2 [4] IR
111 PIO2[3] I/O PIO port 2 [3] TL
110 PIO2[2] I/O PIO port 2 [2] IRQ
109 PIO2[1] I/O PIO port 2 [1] RXD1
108 PIO2[0] I/O PIO port 2 [0] TXD1
12 PIO3[6] I/O PIO port 3 [6] NOTIORD
11 PIO3[5] I/O PIO port 3 [5] NOTIOWR
10 PIO3[4] I/O PIO port 3 [4] CARDDET
7 PIO3[3] I/O PIO port 3 [3] TVSCL
6 PIO3[2] I/O PIO port 3 [2] TVSDA
5 PIO3[1] I/O PIO port 3 [1] I2CSCL
4 PIO3[0] I/O PIO port 3 [0] I2CSDA
Miscellaneous
114 IRB_UHF_IN I UHF channel input for IRB PIO2[4] IR
115 IRB_PPM_OUT O PPM output of IRB PIO2[5] TL
114 IRB_PPM_IN I PPM input of IRB PIO2[4] IR
115 PCM_DATAOUT O PCM data output PIO2[5], alt1 TL
116 PCM_LRCLKOUT O PCM LR clock output PIO2[6], alt1 TL
117 PCM_SCLKOUT O PCM S clock output PIO2[7], alt1 TL
116 FDMA_REQ_0 O Frequency division multiple access PIO2[6], alt0 TL
117 FPRESET I FP_reset signal PIO2[7], alt0 TL
10 EXTINT2 I External input 2 PIO3[4], alt0 CARDDET
11 EXTINT1 I External input 1 PIO3[5], alt0 NOTIOWR
12 EXTINT0 I External input 0 PIO3[6], alt0 NOTIORD
4 DMAREQ(0) O Direct Memory Access request (0) PIO3[0], alt2 I2CSDA
5 DMAREQ(1) O Direct Memory Access request (1) PIO3[1], alt2 I2CSCL
6 EXT_INT_OUT(0) O External input_output (0) PIO3[2], alt2 TVSDA
7 EXT_INT_OUT(1) O External input_output (1) PIO3[3], alt2 TVSCL
Debug link
JTAG test access port (TAP) pins
134 TDI I TAP boundary scan test data input TDI
133 TMS I TAP boundary scan test mode input TMS
137 TCK I TAP boundary scan test clock TCK
135 NOT_TRST I TAP boundary scan test logic reset NOTTRST
132 TDO O TAP boundary scan test data output TDO
DCU pins
1 DCUTRIGGERIN I External trigger input to DCU TRIGIN
2 DCUTRIGGEROUT O Signal to trigger external debug circuitry TRIGOUT
pin Alternative function I/O Description Usual assignment sheet name