HT-M700H
8 – 2
U1A VHiES6698FD-1: Decoder (ES6698FD) (2/3)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input/Output
Function
106
VREF
Input
Internal voltage reference to video DAC.
YUV1
Output
YUV pixel 1 output data.
107
COMP
Input
Compensation input.
YUV3
Output
YUV pixel 3 output data.
108
REST
Input
DAC current adjustment resistor input.
YUV4
Output
YUV pixel 4 output data.
109
FDAC
Output
Video DAC output.
YUV7
Output
YUV pixel 7 output data.
110
VDAC
Output
Video DAC output.
YUV6
Output
YUV pixel 6 output data.
111
VD33_DA
Input
Power for I/O power supply for VDAC.
112
VS33_DA
–
Ground for I/O power supply for VDAC.
113
YDAC
Output
Video DAC output.
YUV5
Output
YUV pixel 5 output data.
114
CDAC
Output
Video DAC output.
YUV2
Output
YUV pixel 2 output data.
115
UDAC
Output
Video DAC output.
YUV0
Output
YUV pixel 0 output data.
116
TWS
Output
Audio transmit frame sync output.
SEL_PLL2
Input
System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencues and their respective PLL bit set-
tings.
Strapped to VCC or ground via 4.7 kohms resistor; read only during reset.
117
TSD0
Output
Audio transmit serial data port 0.
SEL_PLL0
Input
System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencues and their respective PLL bit set-
tings.
Strapped to VCC or ground via 4.7 kohms resistor; read only during reset.
118
TSD1
Output
Audio transmit serial data port 1.
SEL_PLL1
Input
System and DSCK output clock frequency selection is made at the rising edge of RESET#.
The matrix below lists the available clock frequencues and their respective PLL bit set-
tings.
Strapped to VCC or ground via 4.7 kohms resistor; read only during reset.
119
VS33
–
Ground for I/O power supply.
120, 121*
TSD2, TSD3
Output
Audio transmit serial data port 2 and 3.
122
MCLK
Input/Output
Audio master clock for audio DAC.
123
TBCK
Output
Audio transmit bit clock.
124
SPD_DOBM
Output
S/PDIF output.
SEL_PLL3
Input
Clock source select. Strapped to VCC or ground via 4.7 kohms resistor; read only during
reset.
125
SPDIF_IN
Input
S/PDIF input; (5 V tolerant input).
126
VD33
Input
I/O power supply.
127
VS33
–
Ground for I/O power supply.
128
WBLCLK
Output
DVD-RAM wobble detector circuit clock source to preamp.
129
WBL
Output
DVD-RAM wobble output.
130*
LG
Output
DVD-RAM land/groove flag.
131
IP2
Input
DVD-RAM header position index 2.
132
IP1
Input
DVD-RAM header position index 1.
133*-136*
FLAG0-FLAG3
Output
To minitor servo status.
137
VSS
–
Ground for core power supply.
138
VDD
Input
Core power supply.
139
TEXI
Input
High-speed tracking error input.
140
TESTAD
Input
Test AD input.
141
SBAD
Input
Sub-beam addition input signal.
142
FEI
Input
Focus input error signal.
143
AVSS_AD
–
Analog ground for ADC block.
144
CEI
Input
Center error input signal.
145
TEI
Input
Tracking error input signal.
146
RFRP
Input
RF ripple/envelope input signal.
147
AVDD3_AD
Input
Analog power supply for ADC block.
148
VREF21
Output
2.1 V reference voltage.
Содержание HT-M700H
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