Sharp HT-DV40H, Руководство по обслуживанию

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HT-DV40H
8 – 42
IC13 VHIAK4683EQ-1 : MULTI CHANNEL AUDIO CODEC ( AK4683 ) ( 3/3 )
PIN DESCRIPTION
No. Pin Name Input / Output Function
1 PVDD — PLL Power supply Pin, 4.5V~5.5V
2 RX0 Input
Receiver Channel 0 Pin (Internal biased pin. Internally biased at
PVDD/2)
3 I2C Input
Control Mode Select Pin.
“L”: 4-wire Serial, “H”: I
2
C Bus
4 RX1 Input Receiver Channel 1 Pin
5 RX2 Input Receiver Channel 2 Pin
6 RX3 Input Receiver Channel 3 Pin
7 INT Output Interrupt Pin
8
VOUT Output V-bit Output Pin for Receiver Input
DZF Output
Zero Input Detect Pin
When the input data of DAC follow total 8192 LRCK cycles with
“0” input data, this pin goes to “H”. And when RSTN1 bit is “0”,
PWDA bit is “0”, this pin goes to “H”.
OVF Output
Analog Input Overflow Detect Pin
This pin goes to “H” if the analog input of Lch or Rch overflows.
9 CDTO Output Control Data Output Pin in Serial Mode and I2C pin = “L”.
10 LRCKB Input / Output Channel Clock B Pin
11 BICKB Input / Output Audio Serial Data Clock B Pin
12 SDTOB Output Audio Serial Data Output B Pin
13 OLRCKA Input / Output Output Channel Clock A Pin
14 ILRCKA Input / Output Input Channel Clock A Pin
15 BICKA Input / Output Audio Serial Data Clock A Pin
16 SDTOA Output Audio Serial Data Output A Pin
17 MCKO Output Master Clock Output Pin
18 TVDD — Output Buffer Power Supply Pin, 2.7V~5.5V
19 DVSS — Digital Ground Pin, 0V
20 DVDD — Digital Power Supply Pin, 4.5V~5.5V
21 XTI Input X'tal Input Pin
22 XTO Output X'tal Output Pin
23 TX Output
Transmit Channel Output pin
When DIT bit = “0”, RX0~3 Through.
When DIT bit = “1”, Internal DIT Output.
24 MCLK2 Input Master Clock Input Pin
25 PDN Input
Power-Down Mode & Reset Pin
When “L”, the AK4683 is powered-down, all registers are reset.
And then all digital output pins go “L”. The AK4683 must be reset
once upon power-up.
26
CDTI Input Control Data Input Pin in Serial Mode and I2C pin = “L”.
SDA Input / Output Control Data Pin in Serial Mode and I2C pin = “H”.
27
CCLK Input Control Data Clock Pin in Serial Mode and I2C pin = “L”
SCL Input Control Data Clock Pin in Serial Mode and I2C pin = “H”
28
CSN Input Chip Select Pin in Serial Mode and I2C pin = “L”
TEST Input
This pin should be connected to DVSS in Serial Mode and I2C pin
= “H”
29 SDTIA1 Input Audio Serial Data Input A1 Pin
30 SDTIA2 Input Audio Serial Data Input A2 Pin
31 SDTIA3 Input Audio Serial Data Input A3 Pin
32 SDTIB Input Audio Serial Data Input B Pin
33 HVDD — HP Power Supply Pin, 4.5V~5.5V
34 HVSS — HP Ground Pin, 0V
35 HPR Output HP Rch Output Pin
36 HPL Output HP Lch Output Pin
37 MUTET —
HP Common Voltage Output Pin
1
μ
F capacitor should be connected to HVSS externally.
38 LOUT2 Output DAC2 Lch Positive Analog Output Pin
39 ROUT2 Output DAC2 Rch Positive Analog Output Pin
40 LOUT1 Output DAC1 Lch Positive Analog Output Pin
41 ROUT1 Output DAC1 Rch Positive Analog Output Pin
42 VCOM —
DAC/ADC Common Voltage Output Pin
2.2
μ
F capacitor should be connected to AVSS2 externally.
43 AVDD2 — DAC Power Supply Pin, 4.5V~5.5V
44 AVSS2 — DAC Ground Pin, 0V
45 LISEL Output Lch Feedback Resistor Output Pin
46 LOPIN Output Lch Feedback Resistor Input Pin. 0.5 x AVDD1.