Sharp HT-DV40H, Руководство по обслуживанию

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HT-DV40H
8 – 33
IC6 VHISPHE6500P- : HDMI TRANSMITTER, 128 Pin ( SPHE6500P ) ( 2/3 )
PIN CONFIGURATION
IC6 VHISPHE6500P- : HDMI TRANSMITTER, 128 Pin ( SPHE6500P ) ( 3/3 )
PIN DESCRIPTION
64 DVCC18
63 DGND
62 DVCC18
61 DGND
60 DVCC33
59 DGND
58 DVCC18
57 DGND
56 DVCC18
55 DGND
54 DVCC18
53 DGND
52 DGND
51 DVCC18
50 DSCL
49 DSDA
48 HPD
47 RESTN
46 KWP/NC
45 KSCL/NC
44 KSDA/NC
43 DVCC33
42 D0
41 D1
40 D2
39 D3
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
NC
NC
NC
DGND
INT
DGND
GPIO_2_0
GPIO_2_1
GPIO_2_2
NC
DVCC18
DVCC33
CSCL
CSDA
IVS
IHS
DGND
DVCC18
Reserved
DGND
XCLK_OUT
XCLK_IN
DVCC33
SPLLVCC
SPLLRC
102 A
VDD1
101 DAC_REFOUT 100 DAC_FSADJ 99 DAC_VBSP 98 A
VSS1
97 DAC0 96 DAC1 95 A
VDD2
94 A
VSS2
93 DAC2 92 DVCC18 91 DVCC33 90 AHS 89 A
VS
88 GPIO_2_3 87 NC 86 DGND 85 DGND 84 TMDSVCC18 83 HAGND 82 HAGND 81 HPVCC2 80 HAGND 79 TX2+ 78 TX2- 77 HA
VCC
76 TX1+ 75 TX1- 74 HAGND 73 TX0+ 72 TX0- 71 HA
VCC
70 TXC+ 69 TXC- 68 HAGND 67 EXT_SWING 66 HPVCC1 65 HAGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
SPLLGND MCLK SCK WS SD3 SD2 SD1 SD0 SPDIF DGND ICLK_0 DVCC33 ICLK DVCC18 DGND D23 D22 D21 D20 D19 D18 D17 D16 DGND DVCC33 D15 D14 D13 D12 D1
1
D10 D9 D8 DGND D7 D6 D5 D4
SPHE6500
LQFP
Mnemonic Pin# Type Dir. Description
Global
RESTN 47 Schmitt Input HW Reset (low active)
Reserved 122 LVTTL Input Always tie LOW
ICLK_O 11 LVTTL Output Output Selected PLL clock
Clock Interface
XCLK_IN 125 LVTTL Input Crystal Clock Input (27MHz)
XCLK_OUT 124 LVTTL Output Crystal Clock Output
Core I
2
C Interface
CSCL 116 Schmitt Intput I
2
C slave clock
CSDA 117 Schmitt B I
2
C slave data (Open drain output)
Video Interface
ICLK 13 LVTTL Intput Pixel Clock
D0 42 LVTTL B RGB24 interface bit-0 (R[2]) or GPIO_1_0(CCIR656-like link)
D1 41 LVTTL B RGB24 interface bit-1 (R[3]) or GPIO_1_1(CCIR656-like link)
D2 40 LVTTL B RGB24 interface bit-2 (R[4]) or GPIO_1_2(CCIR656-like link)
D3 39 LVTTL B RGB24 interface bit-3 (R[5]) or GPIO_1_3(CCIR656-like link)
D4 38 LVTTL B RGB24 interface bit-4 (R[6]) or GPIO_1_4(CCIR656-like link)
D5 37 LVTTL B RGB24 interface bit-5 (R[7]) or GPIO_1_5(CCIR656-like link)
D6 36 LVTTL B RGB24 interface bit-6 (G[2]) or GPIO_1_6(CCIR656-like link)
D7 35 LVTTL B RGB24 interface bit-7 (G[3]) or GPIO_1_7(CCIR656-like link)
D8 33 LVTTL B RGB24 interface bit-8 (G[4]) or GPIO_1_8(CCIR656-like link)
D9 32 LVTTL B RGB24 interface bit-9 (G[5]) or GPIO_1_9(CCIR656-like link)
D10 31 LVTTL B RGB24 interface bit-10 (G[6]) or GPIO_1_10(CCIR656-like link)
D11 30 LVTTL B RGB24 interface bit-11 (G[7]) or GPIO_1_11(CCIR656-like link)