Sharp DV-500D, Техническое руководство

Страница: 99 / 117

DV-560H
12-6
Pin No. Terminal name I/O Operation function Remarks
52 SEL O
53 FLGA O
54 FLGB O
55 FLGC O
56 FLGD O
57 VDD –
58 VSS –
59 IO0 I/O General use I/O port.
60 IO1 It is possible to select the input port and output port according
to command.
61 IO2 In case of input port the terminal state (H/L) can be read with
the read command.
62 IO3 In case of output port the terminal state (H/L/HiZ) can be
controlled with the command.
63 /DMOUT Terminal to set the mode to output dual value PWM of feed
equalizer from the IO0,1 terminal and to output the dual value
PWM from disc equalizer of IO2,3 terminal “L” Active.
64 /CKSE X’tal selection terminal.
When 16.9344 MHz: “H” When 33.8688 MHz: “L”
65 /DACT Test terminal.
66 TESIN Test input terminal.
67 TESIO1 Test input/output terminal.
68 VSS Digital ground terminal.
69 PXI DSP system clock oscillation circuit input terminal.
70 PXO DSP system clock oscillation circuit output terminal.
71 VDD D power terminal.
72 XVSS Ground terminal for system clock oscillation circuit.
73 XI System clock oscillation circuit input terminal.
74 XO System clock oscillation circuit output terminal.
75 XVDD Positive power terminal for system clock oscillation circuit.
76 DVDD – D/A converting section power terminal.
77 RO O R channel data forward rotation output terminal.
78 DVSS – D/A converting section analog ground terminal.
79 DVR – D/A converting section reference voltage terminal.
80 LO O L channel data forward rotation output terminal.
81 DVDD – D/A converting section power terminal.
82 TEST1 I Test terminal. Pull-up resistor
To be opened usually. built in.
83 TEST2 I Test terminal. Pull-up resistor
To be opened usually. built in.
84 TEST3 I Test terminal. Pull-up resistor
To be opened usually. built in.
85 BUS0 I/O Microcomputer interface data input/output terminal. Schmidt input
86 BUS1 I/O CMOS port
87 BUS2 I/O
88 BUS3 I/O
89 VDD – D power terminal.