Sharp DV-500D, Техническое руководство

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DV-560H
12-11. IC2002, IC2003 AMP
Bias
Clamp
1
8
V
IN
1
V
IN
2
2.07K
Ω
2.2K
Ω
6.2dB
Amp
75
Ω
Driver
2.07K
Ω
2.2K
Ω
6.2dB
Amp
75
Ω
Driver
7
V
+
5
6
4
3
NC
V
OUT
1
V
OUT
2
V
SAG
1
750
Ω
2
GND
SAG correction terminal
12-12. IC402 IX1474GE DEM/ECC (DVD)
Pin No. Terminal name I/O Operation function Remarks
1 DPCK1 I Signal processing reference clock input. 0.5-3.3Vp-p Feedback
resistor built in.
2 DVDD3 – Digital power. (3.3V) For logic cell
3 SVCK1 I Servo reference clock input. (Oscillation circuit input terminal) 3.3V-I/F Feedback
4 SVCK0 O Servo reference clock output. (Oscillation circuit input terminal) resistor built in.
5 DVSS – Digital power. (0V) For logic cell
6 DVDD2 – Digital power. (3.3V) For logic cell
7 N.C. – User use prohibited. Open
8 HDWT I MPU write signal. TTL level
9 HDRD I MPU read signal. TTL level
10 HCEN I MPU chip selection. TTL level
11 HD0 I/O MPU data bus. TTL level
12 HD1 I/O MPU data bus. TTL level
13 HD2 I/O MPU data bus. TTL level
14 HD3 I/O MPU data bus. TTL level
15 HD4 I/O MPU data bus. TTL level
16 HD5 I/O MPU data bus. TTL level
17 HD6 I/O MPU data bus. TTL level
18 HD7 I/O MPU data bus. TTL level
19 DVSS – Digital power. (0V) For I/O cell
20 DVDD5 – Digital power. (5V) For I/O cell
21 HINT O MPU interruption signal. (Occurrence of interruption = “L”) OPEN DRAIN
22 HA0 I MPU address bus. TTL level
23 HA1 I MPU address bus. TTL level
24 PLCK I/O Read channel clock input/output terminal.
12-20