Sharp AQUOS LC-42XD10E, Руководство по обслуживанию

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LC-42XD10E/RU
5 – 24
AA4 VDDAADAC - 3.3 V power for audio DAC VDDADC
A
AA2 VSSAADAC - Ground for audio DAC command switches GNDA-
DAC
Y4 VDDASADAC - 3.3 V power for audio DAC substrate VDDA-
DAC
AB2 VCCAADAC - 3.3 V power for audio DAC command switches VDDA
AB3 GNDAADAC - Ground for audio DAC GNDA-
DAC
AC2 VCCASADAC - 3.3 V power for audio DAC command switches
substrate
VDDA
AD2 IREF I Audio DAC output reference current
AE2 VBGFIL I Audio DAC filtered output reference voltage VBGFIL
AF4 LPCLKIN I Low power clock input (1.8 V tolerant) CLOCK
IN
AF5 LPCLKOSC I/O Low power clock oscillator (1.8 V tolerant) CLOCK
A16 NO32XTAL1 I Select for 32 kHz clock source
0: XTAL, 1: Internal divider
TCK
A13 CLK27MA I Selectable input clock to PLL or for x1 mode (5 V tolerant) CLK27MH
Z
A11 CLKSPEEDSEL I PLL speed select (5 V tolerant)
A12 AUXCLKOUT O Auxiliary clock for general use (5 V tolerant)
AF6 notRESET I System reset (1.8 V tolerant) SYSRE-
SET
AD14 notWDOGRSTOUT O Internal watchdog timer reset (5 V tolerant)
AE14 TDI I Boundary scan test data input (5 V tolerant) TDI
AC14 TMS I Boundary scan test mode select (5 V tolerant) TMS
AF16 TCK I Boundary scan test clock (5 V tolerant) TCK
AF14 notTRST I Boundary scan test logic reset (5 V tolerant) NOT-
TRST
AE13 TDO O Boundary scan test data output (5 V tolerant) TDO
P1 DCUTRIGGERIN I External trigger input to DCU (5 V tolerant) TRIGIN
P3 DCUTRIGGEROUT O Signal to trigger external debug circuitry (5 V tolerant) TRIGOUT
C23 TSIN2LBYTECLK I/O Transport stream bit clock (5 V tolerant) TS2CLK
C22 TSIN2LBYTECLKVA
LID I/O Transport stream bit clock valid edge (5 V tolerant) TS2VAL
B23 TSIN2LERROR I/O Transport stream packet error (5 V tolerant)
D19 TSIN2LPACKETCLK I/O Transport stream packet strobe (5 V tolerant) TS2STRT
B18,C18,D18,C19,C20,D20,
C21,D21 TSIN2LDATA[7:0] I/O Transport stream data (5 V tolerant) TS2D[7:0]
P23 TSIN1BYTECLK I Transport stream bit/byte clock (5 V tolerant) FECLK
M24 TSIN1BYTECLKVALI
D I Transport stream bit/byte clock valid edge (5 V tolerant) FEVALID
M26 TSIN1ERROR I Transport stream packet error (5 V tolerant) FEER-
ROR
N26 TSIN1PACKETCLK I Transport stream packet strobe (5 V tolerant) FES-
TROUT
K26,J25,H24,J24,L26,L25,L
24,M23 TSIN1DATA[7:0] I Transport stream data in (5 V tolerant) FED[7:0]
L3 notEMIRAS or
notCI_IORD1 O Row address strobe for SDRAM EMIRAS
K1 not_EMICAS or
not_CI_IOW1 O Column address strobe for SDRAM EMICAS
J1 notEMICSA O Peripheral chip select A EMICSO
K3 notEMICSB O Peripheral chip select B
K2 notEMICSC O Peripheral chip select C
N4 notEMICSD O Peripheral chip select D EMICS3
J2 notEMICSE O Peripheral chip select E
L2 notEMICSF O Peripheral chip select F EMICS5
L1, N3 notEMIBE[1:0] O External device data bus byte enable. 1 bit per byte of the data bus. EMIBE1,
EMIRAS
N1 notEMIOE or
not_CI_OE O External device output enable. EMIOE
N2 notEMILBA or
notCI_Wea O Flash device load burst address. EMILBA
P4 EMIWAITnot-
TREADY I External memory device target ready indicator (5 V tolerant) CPUWAIT