Sharp Aquos LC-37D90U, Руководство по обслуживанию

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LC-37D90U
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B10 DMAREQ_CH0n O External DMA Request Signal-Channel 0. The RH-IXB323WJZZ will drive this signal low when it is
ready for the system DMA controller. This signal is hi-Z when not driven low.
A13 DMAACK_CH0n I External DMA Acknowledge Signal-Channel 0. The system DMA controller will drive this high when
it has received DMAREQ_CH0n signal and is ready to transfer data. The RH-IXB323WJZZ stop
driving the DMAREQ_CH0n signal once this signal is received.
D10 DMAREQ_CH1n O External DMA Request Signal-Channel 1. The RH-IXB323WJZZ drive this signal low when it is
ready for the system DMA controller. This signal is hi-Z when not driven low.
C9 DMAACK_CH1n I External DMA Acknowledge Signal-Channel 1. The system DMA controller will drive this high when
it has received the DMAREQ_CH1n signal and is ready to transfer data. The RH-IXB323WJZZ stop
driving the DMAREQ_CH1n signal once this signal is received.
HSDI0
Note: If this port is not used, all HSD1 signals can be tied to GND as long as HSDI0Cfg. Enable is set to 0.
G13 HSDIO_CLKz I/O HSDI Port 0 Clock. All signals and data on HSDI Port 0 are clocked using this clock.
G10 HSDIO_SYNCz I/O HSDI port 0 synchronization signal. This signal is used to indicate the start of packet (or MPEG2
cell.)
For transmit onto 1394, this signal is input to the RH-IXB323WJZZ from the system with the data.
For receive from 1394, the RH-IXB323WJZZ outputs this signal with the data.
If not used in transmit mode, this signal can be tied low.
G11 HSDIO_DVALIDz
(HSDIO_ENz) I/O HSDI port 0 Data Valid Pin. This pin indicate if data on the HSDI data bus is valid for reading or writ-
ing.
For transmit onto 1394, this signal is input to the RH-IXB323WJZZ by the system with the data.
For receive from 1394, the RH-IXB323WJZZ outputs this signal with the data.
If not used in transmit mode, this signal can be tied low.
HSDI port 0 enable pin (HSDI0_Enz) in HSDI RX mode 8/9 (celynx sync mode B compatible
modes).
This signal is always an input in HSDI RX mode 8/9. This signal indicates whether data can be
driven onto the HASID bus. (i.e. if HSDI0_ENz is disserted, HSDI0 data bus and HSDI0 sync will be
tri-stated).
G14 HSDIO_ERRORz
(HSDI0_FrameSyncz) I/O HSDI port 0 Error pin in MPEG2-DSS mode. This signal is used to indicate the value of the TS error
bit in the 10 bytes DSS header.
HSDI1_Frame Sync pin HSDI DV mode (TX modes 6/7, RX modes 6-9). This signal is used to indi-
cate the start of DV frames.
This pin is not used in MPEG2-DVB mode. This signal can be left open when HSDI0 is programmed
for RX direction (1394 RX) only. This signal should be pulled up/down when HSDI0 is programmed
for TX direction (1394 TX) or used for both directions.
M10 DSSCIK27 I DSS 27MHz system clock count. The 27MHz clock input on this pin is used to generate the SCC
timestamp in the DSS 10 bytes header.
This pin is used to generate the SCC field for all three HSDI ports (HSDI0, HSDI1, and HSDI2.)
This pin is valid on MPEG2-DSS transmit only. This pin can be tied directly to GND in other video or
audio modes.
D14 HSDIO_D0 I/O HSDI port 0 data 0 pin. Data 0 is the least significant bit on the HSDI data bus.
In serial mode, only HSDI0_D [0] is used, HSDI0_D [7:1] are not used.
E13 HSDIO_D1 I/O HSDI port 0 data 1 pin. In HSDI transmit serial mode (1394 TX), HSDI0_D [7:1] are in don't care sta-
tus. In HSDI receive serial mode (1394 RX), HSDI0_D [7:1] are Hi-Z. In serial mode, HSDI0_D [7:1]
can be tied directly to GND.
E14 HSDIO_D2 I/O HSDI Port 0 Data 2 Pin.
(For serial mode operation, see PIN description for HSDI0_D1 above.)
E12 HSDIO_D3 I/O HSDI Port 0 Data 3 Pin.
(For serial mode operation, see PIN description for HSDI0_D1 above.)
E11 HSDIO_D4 I/O HSDI Port 0 Data 4 Pin.
(For serial mode operation, see PIN description for HSDI0_D1 above.)
F10 HSDIO_D5 I/O HSDI Port 0 Data 5 Pin.
(For serial mode operation, see PIN description for HSDI0_D1 above.)
F12 HSDIO_D6 I/O HSDI Port 0 Data 6 Pin.
(For serial mode operation, see PIN description for HSDI0_D1 above.)
F11 HSDIO_D7 I/O HSDI Port 0 Data 7 Pin. Data 7 is the most significant bit on the HSDI data bus.
(For serial mode operation, see PIN description for HSDI0_D1 above.)
HSDI1
Note: If this port is not used, all HSD1 signals can be tied to GND as long as HSDI1Cfg. Enable is set to 0.
L12 HSDI1_CLKz I/O HSDI port 1 clock. All signal and data on HSDI port 1 are clocked using this clock.
K12 HSDI1_SYNCz I/O HSDI port 1 synchronization signal. This signal is used to indicate the start of packet (or MPEG2
cell.)
For transmit onto 1394, this signal is input to the RH-IXB323WJZZQ from the system with the data.
For receive from 1394, the RH-IXB323WJZZQ outputs this signal with the data.
If not used in transmit mode, this signal can be tied low.
Pin No. Pin Name I/O Pin Function