Sharp Aquos LC-32AX3X, Руководство по обслуживанию

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LC-32AX3H/M/X
LC-37AX3H/M/X
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IC1203 (MM1630AQ)
Under control of the I2C bus, this video switch serves to switch between two-line color difference signals
(component signals), one-line S video signal and four-line composite signals. The analog video signals coming
from the input terminals and the tuner are fed into this IC for selection. The video output signal and component
video signal from this IC are supplied to the video processor circuit IC3300 (IXB405WJ).
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IC3301 (IXB405WJ)
This video processor consists of a VLSI system-on-chip device. It is equipped with a high-precision, 108-MHz,
10-bit ADC (Analog Digital Converter) for speedy data processing. For analog video processing, it supports a
high-performance, multi-format 3D digital Y/C separation video decoder for the NTSC system, and a motion-
adaptive de-interlacing engine as well as a video format conversion engine for the PAL and SECAM systems.
10-bit video signals are processed from the input stage up to the video output stage.
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IC4501 (IXB375WJ)
The EEPROM IC is intended to store LUT (Look-Up-Table) for the IC3301 (IXB405WJ) video processor.
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IC3201 (DS90CF386)
The DS90CF386 is an LVDS (Low Voltage Differential Signaling) receiver for communication with the IC3301
(IXB405WJ) video processor at the preceding stage. It converts 4-pair LVDS data stream to 28-bit CMOS/TTL
parallel data (24-bit RGB signals as well as 4-bit HSYNC, VSYNC, DE and CNTL signals). The HSYNC and
VSYNC signals, which are video output sync signals, are fed to the IC1503 (IXB497WJ) CPLD-2 (Complex
Programmable Logic Device) to generate the inverter circuit trigger pulse.
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IC3202 (DS90C385A)
The DS90C385A receives the video signal from the IC3201 (DS90CF386) LVDS receiver at the preceding
stage and feeds out the LVDS signal to the LCD controller at the next stage. Technically, a communication
programmable LVDS transmitter works to convert 28-bit LVCMOS/LVTTL input parallel data to 4-pair LVDS
serial data. The clock signal too gets phase-adjusted in the transmitter PLL circuit to become one-pair LVDS
data. The 28-bit input data is sampled in each cycle of clock signal and then transmitted.
When the clock frequency is at 85 MHz, the 24-bit RGB data and the 3-bit LCD timing and control signals
(FPLINE, FPFRAME and DRDY) are transmitted at 595 Mbps per channel of LVDS data. In other words, the
total transmission rate is 297.5 MB/s.
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IC1014 (IXB496WJ)
The CPLD-1 (Complex Programmable Logic Device) provides for the main microprocessor's extension inputs
and outputs and other functions. The CS1 is commonly used for the CPLD-1 and CPLD-2, which means that
the IC1503 (IXB497WJ) CPLD-2 is under the same control. Some addresses to access are handled automatically
inside the CPLD_1, whereas the addresses assigned to the CPLD_2 are accessed by going through the CPLD_1
up to the CPLD_2. For this purpose, the CS is connected in series with the CPLD_2 along the RD and WR
control lines as well as the address and data buses. This IC, which behaves in sync with the IC1001 (IXB427WJ)
microprocessor, runs on backup power.
MAJOR IC INFORMATIONS