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43 CHAPTER 7 Interrupt and exception handling with CMSIS
7.7 Interrupt and exception handling with CMSIS
The embOS CPU specific projects come with CPU specific vector tables and empty exception
and interrupt handlers for the specific CPU. All handlers are named according the names
of the CMSIS device specific handlers and are declared weak and can be replaced by an
implementation in the application source files. The CPU specific vector table and interrupt
handler functions in the embOS start projects can be replaced by the CPU specific CMSIS
startup file of the CPU vendor without any modification on other files in the project. embOS
uses the two Cortex-M generic exceptions PendSV and SysTick and delivers its own handler
functions to handle these exceptions. All peripheral interrupts are device specific and are
not used with embOS except for profiling support and system analysis with embOSView
using a UART.
7.7.1 Enable and disable interrupts
The generic CMSIS functions
NVIC_EnableIRQ()
and
NVIC_DisableIRQ()
can be used in-
stead of the embOS functions
OS_ARM_EnableISR()
and
OS_ARM_DisableISR()
functions.
Note that the CMSIS functions use different peripheral ID indices to address the specific
interrupt number. embOS counts from 0 for the first entry in the interrupt vector table,
CMSIS counts from 0 for the first peripheral interrupt vector, which is ID number 16 for
the embOS functions. About these differences, please refer to Different peripheral ID num-
bers on page 42. To enable and disable interrupts in general, the embOS functions
OS_IN-
T_IncDI()
and
OS_INT_DecRI()
or other embOS functions described in the generic embOS
manual should be used instead of the intrinsic functions from the CMSIS library.
7.7.2 Setting the Interrupt priority
With CMSIS, the CMSIS generic function
NVIC_SetPriority()
can be used instead of the
OS_ARM_ISRSetPrio()
function. Note that with the CMSIS function, the range of valid in-
terrupt priority values depends on the number of priority bits defined and implemented
for the specific device. The number of priority bits for the specific device shall be defined
in the device specific CMSIS header file as
__NVIC_PRIO_BITS
. If it is not defined in the
device specific header files, a default of 4 is set in the generic CMSIS core header file. A
CPU with 4 priority bits supports up to 16 preemption levels. With CMSIS, the range of
interrupt priorities for this CPU would be 0 to 15, where 0 is the highest priority and 15 is
the lowest. About interrupt priorities in an embOS project, please refer to Interrupt priori-
ties on page 31 and Interrupt nesting on page 32, about the differences between interrupt
priority and ID values used to setup the NVIC controller, please refer to Different interrupt
priority values on page 42.
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