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42 CHAPTER 7 Adding CMSIS to other embOS start projects
tialize the core clock system and pll of the specific CPU. The system clock frequency and
core clock frequency are defined in the RTOSInit file. If the application needs access to
the
SystemCoreClock
, the core specific CMSIS startup code and core specific initialization
function
SystemInit
has to be included in the project. In this case,
OS_InitHW()
function
in RTOSInit may be replaced, or the CMSIS generic
RTOSInit_CMSIS.c
file may be used
in the project.
7.6.1 Differences between embOS projects and CMSIS
Several embOS start projects are not based on CMSIS but are fully CMSIS compliant and can
be mixed with CMSIS libraries from the device vendors. Switching from embOS to CMSIS,
or mixing embOS with CMSIS functions is possible without problems, but may require some
modification when the interrupt controller setup functions from CMSIS shall be used instead
of the embOS functions.
7.6.1.1 Different peripheral ID numbers
Using CMSIS, the peripheral IDs to setup the interrupt controller start from 0 for the first
peripheral interrupt. With embOS, the first peripheral is addressed with ID number 16.
embOS counts the first entry in the interrupt vector table from 0, so, the first peripheral
interrupt following the 16 Cortex system interrupt entries, is 16. When the embOS functions
should be replaced by the CMSIS functions, this correction has to be taken into account, or
if available, the symbolic peripheral id numbers from the CPU specific CMSIS device header
file may be used with CMSIS. Note that using these IDs with the embOS functions will work
only, when 16 is added to the IDs from the CMSIS device header files.
7.6.1.2 Different interrupt priority values
Using embOS functions, the interrupt priority value ranges from 0 to 255 and is written
into the NVIC control registers as is, regardless of the number of implemented priority bits.
255 is the lowest priority, 0 is the highest priority. Using CMSIS, the range of interrupt
priority levels used to setup the interrupt controller depends on the number of priority bits
implemented in the specific CPU. The number of priority bits for the specific device shall be
defined in the device specific CMSIS header file as
__NVIC_PRIO_BITS
. If it is not defined
in the device specific header files, a default of 4 is set in the generic CMSIS core header
file. A CPU with 4 priority bits supports up to 16 preemption levels. With CMSIS, the range
of interrupt priorities for this CPU would be 0 to 15, where 0 is the highest priority and
15 is the lowest. To convert an embOS priority value into a value for the CMSIS functions,
the value has to be shifted to the right by (
8 - __NVIC_PRIO_BITS
). To convert an CMSIS
value for the interrupt priority into the value used with the embOS functions, the value has
to be shifted to the left by (
8 - __NVIC_PRIO_BITS
). In any case, half of the priorities
with lower values (from zero) are high priorities which must not be used with any interrupt
handler using embOS functions.
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