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31 CHAPTER 6 Interrupt-stack switching
6.4 Interrupt-stack switching
Since Cortex-M core based controllers have two separate stack pointers and embOS utilizes
the process stack pointer to execute tasks, there is no need to explicitly switch stacks inside
interrupt routines, which utilize the main stack pointer. The routines
OS_INT_EnterIntS-
tack()
and
OS_INT_LeaveIntStack()
are supplied for source code compatibility to other
processors only and have no functionality.
6.5 Zero latency interrupts
Instead of disabling interrupts when embOS does atomic operations, the interrupt level
of the CPU is set to 128. Therefore, all interrupt priorities higher than 128 can still be
processed (please note that lower priority numbers define a higher priority). Interrupts with
priority level from 0 to 127 are never disabled. These interrupts are named zero latency
interrupts. You must not execute any embOS function from within a zero latency interrupt.
Note
Please be aware with ARM Erratum 837070 embOS sets the PRIMASK before writing to
BASEPRI and unconditionally clears it afterwards. Therefore, zero lateny interrupts are
disabled for a few cycles when embOS disables or enables embOS interrupts. Please
have a look in the chapter ARM erratum 837070 for more details.
6.6 Interrupt priorities
This chapter describes interrupt priorities supported by the Cortex-M core. The priority is
any number between 0 and 255 as seen by the CPU core. With embOS and its own setup
functions for the interrupt controller and priorities, there is no difference in the priority
values regardless of the different preemption level of specific devices. Using the CMSIS
functions to set up interrupt priorities requires different values for the priorities. These
values depend on the number of preemption levels of the specific chip. A description is
found in the chapter CMSIS.
6.6.1 Interrupt priorities with Cortex-M cores
The Cortex-M supports up to 256 levels of programmable priority with a maximum of 128
levels of preemption. Most Cortex-M chips have fewer supported levels, for example 8, 16,
32, and so on. The chip designer can customize the chip to obtain the levels required. There
is a minimum of 8 preemption levels. Every interrupt with a higher preemption level may
preempt any other interrupt handler running on a lower preemption level. Interrupts with
equal preemption level may not preempt each other.
With introduction of zero latency interrupts, interrupt priorities usable for interrupts using
embOS API functions are limited.
• Any interrupt handler using embOS API functions has to run with interrupt
priorities from 128 to 255. These embOS interrupt handlers have to start with
OS_INT_Enter()
or
OS_INT_EnterNestable()
and have to end with
OS_INT_Leave()
or
OS_INT_LeaveNestable()
.
• Any zero latency interrupt (running at priorities from 0 to 127) must not call any embOS
API function. Even
OS_INT_Enter()
and
OS_INT_Leave()
must not be called.
• Interrupt handlers running at low priorities (from 128 to 255) not calling any embOS
API function are allowed, but must not re-enable interrupts! The priority limit between
embOS interrupts and zero latency interrupts is fixed to 128 and can only be changed
by recompiling embOS libraries! This is done for efficiency reasons. Basically the define
OS_IPL_DI_DEFAULT
in
RTOS.h
and the
RTOS.s
file must be modified. There might be
other modifications necessary. Please contact the embOS support if you like to change
this threshold.
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