SM-B69
SM-B69 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.1 - Author:A.R - Reviewed by M.B. - Copyright © 2020 SECO S.p.A.
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3.2.1.13
PCI Express interface signals
The SM-B69 module can offer externally four PCI Express lane, which are directly managed by the Intel® family of SOCs formerly coded as Apollo Lake.
PCI express Gen 2.0 (5Gbps) is supported.
Here following the signals involved in PCI express management
PC/ PCIE_A_RX-: PCI Express lane #0, Receiving Input Differential pair
PC/PCIE_A_TX-: PCI Express lane #0, Transmitting Output Differential pair
PCIE_/ PCIE_A_REFCK-: PCI Express Reference Clock for lane #0, Differential Pair
PCIE_A_RST#: Reset Signal that is sent from SMARC Module to a PCI-e device available on the carrier board. Active Low, +3.3V_ALW electrical level. it can be
used directly to drive externally a single RESET Signal. In case Reset signal is needed for multiple devices, it is recommended to provide for a buffer on the carrier
board.
PCIE_A_CKREQ#: PCI Express Port A clock request signal, used from a PCI-e device to request the need for PCI Express Reference Clock. Bidirectional signal,
+3.3V_RUN electrical level with a 20k pull-up resistor.
PC/ PCIE_B_RX-: PCI Express lane #1, Receiving Input Differential pair
PC/PCIE_B_TX-: PCI Express lane #1, Transmitting Output Differential pair
PCIE_/ PCIE_B_REFCK-: PCI Express Reference Clock for lane #1, Differential Pair
PCIE_B_RST#: Reset Signal that is sent from SMARC Module to a PCI-e device available on the carrier board. Active Low, +3.3V_ALW electrical level. it can be
used directly to drive externally a single RESET Signal. In case Reset signal is needed for multiple devices, it is recommended to provide for a buffer on the carrier
board. This signal is shared
PCIE_B_CKREQ#: PCI Express Port B clock request signal, used from a PCI-e device to request the need for PCI Express Reference Clock. Bidirectional signal,
+3.3V_RUN electrical level with a 20k pull-up resistor.
PC/ PCIE_C_RX-: PCI Express lane #2, Receiving Input Differential pair
PC/PCIE_C_TX-: PCI Express lane #2, Transmitting Output Differential pair
PCIE_/ PCIE_C_REFCK-: PCI Express Reference Clock for lane #2, Differential Pair
PCIE_C_RST#: Reset Signal that is sent from SMARC Module to a PCI-e device available on the carrier board. Active Low, +3.3V_ALW electrical level. it can be
used directly to drive externally a single RESET Signal. In case Reset signal is needed for multiple devices, it is recommended to provide for a buffer on the carrier
board.
PC/ PCIE_D_RX-: PCI Express lane #3, Receiving Input Differential pair
PC/PCIE_D_TX-: PCI Express lane #3, Transmitting Output Differential pair
PCIE_WAKE#: PCIe wake up interrupt to host input signal. Active low, +3.3V_ALW electrical level with a 10k pull-up resistor.
In the following table are shown the possible groupings allowed of the PCI-e lanes:
