SBC-C41-pITX
SBC-C41-pITX User Manual - Rev. First Edition: 1.0 - Last Edition: 1.1 - Author: A.R./S.B. - Reviewed by M.B. Copyright © 2021 SECO S.p.A.
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4.3.16.1
LVDS Advanced options submenu
Menu Item
Options
Description
Spreading Depth
No Spreading / 0.5% /
1.0% / 1.5% / 2.0% /
2.5%
Sets percentage of bandwidth of LVDS clock frequency for spreading spectrum
Output Swing
150 mV / 200 mV / 250
mV / 300 mV / 350 mV /
400 mV / 450 mV
Sets the LVDS differential output swing
T3 Timing
0 ÷ 255
Minimum T3 timing of panel power sequence to enforce (expressed in units of 50ms). Default is 10
(500ms)
T4 Timing
0 ÷ 255
Minimum T4 timing of panel power sequence to enforce (expressed in units of 50ms). Default is 2 (100ms)
T12 Timing
0 ÷ 255
Minimum T12 timing of panel power sequence to enforce (expressed in units of 50ms). Default is 20 (1s)
T2 Delay
Enabled / Disabled
When Enabled, T2 is delayed by 20ms ± 50%
T5 Delay
Enabled / Disabled
When Enabled, T5 is delayed by 20ms ± 50%
P/N Pairs Swapping
Enabled / Disabled
Enable or disable LVDS Differential pairs swapping (Positive
Negative)
Pairs Order Swapping
Enabled / Disabled
Enable or disable channel differential pairs order swapping (A
D, B
CLK, C
C)
LVDS BUS Swapping
Enabled / Disabled
Enable or disable Bus swapping (Odd
Even)
Firmware PLL
0: +/- 1.56%
1: +/- 3.12%
2: +/- 6.25%
3: +/- 12.5%
4: +/- 25%
5: +/- 50%
6: +/- 100%
Set Firmware PLL range
LFP V-Sync Polarity
Negative / Positive
Vertical Sync Polarity: Default is Negative (Active Low)
LFP H-Sync Polarity
Negative / Positive
Horizontal Sync Polarity: Default is Negative (Active Low)
LVDS Advanced Options
See Submenu
LVDS Advanced Options Configurations
