SBC-C41-pITX
SBC-C41-pITX User Manual - Rev. First Edition: 1.0 - Last Edition: 1.1 - Author: A.R./S.B. - Reviewed by M.B. Copyright © 2021 SECO S.p.A.
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US/USB_SSTX2-: USB Super Speed Port #2 transmit differential pair; it is managed by xHCI controller
S/SATA0_TX-: Serial ATA Channel #0 Transmit differential pair
S/SATA0_RX-: Serial ATA Channel #0 Receive differential pair
PWR_OFF#: Power Off signal for plugged modules, usually used in battery-
-up @ 3.3V_ALW
KEYB_W_DISABLE1#: M.2 Key B module disable signal #1, 3.3V_ALW active low output
KEYB_W_DISABLE2#: M.2 Key B module disable signal #2, 3.3V_ALW active low output
UIM_RESET: Reset signal line, sent from M.2 WWAN card to the UIM module.
UIM_DATA: Bidirectional Data line between M.2 WWAN card and UIM module.
UIM_CLK: Clock line, output from M.2 WWAN card to the UIM module.
UIM_PWR: Power line for UIM module.
PLT_RST#: Reset Signal that is sent from the SoC to all devices available on the board (i.e. the GbE controllers and the modules plugged in the CN15 slot). It is a
3.3V active-low signal with 100k
Ω
pull-down.
CONFIG_[0..3]: Configuration inputs, +3.3V_ALW signals with 10k
Ω
pull-up. These signals are used to configure properly the Main Host interface according to the
Add-In Card plugged in CN14 Slot. These configuration pins are managed according to PCI Express M.2 Specifications Table 5.5. Only SATA SSDs and WWAN
USB3.1 modules are supported.
