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For COMMAND, MESSAGE, and STATUS phases, the DB(P_CRCA) signal shall indicate odd parity for DB(7-
0). The DB(P1) signal shall not be checked.
For ST DATA phases, the DB(P_CRCA) signal shall indicate odd parity for DB(7-0). If 8-bit transfers are
enabled, the DB(P1) signal shall not be checked. If 16-bit data transfers are enabled, the DB(P1) signal shall
indicate odd parity for DB(15-8). If 16-bit transfers are enabled and the last information byte transferred does
not fall on the DB(15-8) signals, DB(P1) shall be valid for whatever data is placed on the bus.
Parity protection is not enabled during DT DATA phases.
3.12.3
DT data bus protection using CRC
3.12.3.1
DT data bus protection using CRC overview
When pCRC protection or iuCRC protection are enabled, the error detecting code is a 32-bit (four byte) Cyclic
Redundancy Check (CRC), referred to as CRC-32. It is also used by several other device I/O standards. Four
CRC bytes are transferred with data to increase the reliability of data transfers.
3.12.3.2
Error detection capabilities
The CRC detects all single bit errors, any two bits in error, or any combination of errors within a single 32-bit
range.
3.12.3.3
Order of bytes in the CRC field
Figure 74 of ANSI SCSI Parallel Interface (SPI-5), T10/1525D, shows how transmitted data is used to calculate
the CRC and how the CRC information is then transmitted.
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