Seagate Medalist ST31082A, Руководство по эксплуатации продукта

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Technical Reference Manual Page 31
Register Addresses and Functions
6
Host Address Decoding
The host computer addresses the drive using programmed I/O. This method
requires that:
• a proper chip select be asserted
• the desired register address be placed on the three host address lines
(HA2 - HA0)
• a Read or Write strobe (-HOST IOR/-HOST IOW) is given to the chip
The host generates two independent chip selects on the interface.
• The high order chip select, -HOST CS1, is used to access register 3F6 or
3F7.
• The low order chip select, -HOST CS0, is used to address registers 1F0
through 1F7.
ECC bytes are transferred on bits 7 - 0.
The host data bus 15 - 8 is only enabled when:
• -IO16 is active
• the host is addressing the data register for transferring data
• the host is not transferring ECC bytes, which are only transferred if the
operation is a Read Long or Write Long
The I/O map on the next page defines all of the register addresses and the
functions for these I/O locations.
The sections that follow the I/O map describe each of the registers.