7
Control & Status Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit
0 0 0 0 0 0 0 0 0
IRQ1
B
IRQ1
A
IPWAI
T
TM
STAT
RST
STAT
IRQ0
B
IRQ0
A
Read
X X X X X X X X X X X X X X TM
RST
IP
RST
Write
0 0 0 0 0 0 1 0 0
IRQ1
B
IRQ1
A
0 0 0
IRQ0
B
IRQ0
A
Reset
6
IntReq1 B
IRQ1 B
R
This bit is set high when an IntReq1for IP slot B is asserted. It is cleared when the
interrupt is cleared. This bit is not latched on the Flex/104A.
5
IntReq1 A
IRQ1 A
R
This bit is set high when an IntReq1for IP slot A is asserted. It is cleared when the
interrupt is cleared. This bit is not latched on the Flex/104A.
4
IP Wait
IP Wait
R
This bit indicates whether or not an IP access is in progress. When this bit is one, an IP
access is in progress; otherwise, this bit is zero. Resets to zero.
3
Time Out Status
TM Status
R
This bit is asserted if an IP access has timed out. When an access is started, a timer
internal to the Flex/104A is enabled. If, after 64
µ
s, an acknowledge has not been
detected from the IP, the Flex/104A terminates the access and sets this bit high. To clear
this bit, a one must be written to bit 1 of the Control and Status Register. Resets to zero.
2
IP Reset Status
RST STAT
R
When this bit is asserted low, an IP reset is in progress; otherwise, this bit is high.
Resetting the IP bus requires approximately 250 ms.
1
Reset Time Out Status
TM RST
W
Writing a one to this bit resets the time out counter on board the Flex/104A.
1
IntReq0 B
IRQ0 B
R
This bit is set high when an IntReq0for IP slot B is asserted. It is cleared when the
interrupt is cleared. This bit is not latched on the Flex/104A.
0
IP Reset
IP RST
W
Writing a one to this bit generates an IP Reset* that lasts approximately 250 ms.
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