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wanPTMC-256T3

High-Performance PTMC Communications Controller

Hardware Technical Reference, Rev. 0.A, August 5, 2002

Primary Text Number

M8258

SBE, Inc.

2305 Camino Ramon #200, San Ramon, California 94583
(925) 355-2000

Technical Support (800) 444-0990

Fax: (925) 355-2020

FaxBack Service: (800) 214-4723

Website: http://www.sbei.com

Содержание wanPTMC-256T3

Страница 1: ...re Technical Reference Rev 0 A August 5 2002 Primary Text Number M8258 SBE Inc SBE Inc SBE Inc SBE Inc 2305 Camino Ramon 200 San Ramon California 94583 925 355 2000 Technical Support 800 444 0990 Fax...

Страница 2: ...responsible for damage resulting from information herein All specifications are subject to change without notice SBE Inc and the SBE logo are trademarks of SBE Inc All other trademarks and copyrights...

Страница 3: ...16 Framer 16 Line Interface Unit 16 T8110 time slot interchanger 16 3 2 Compatibility 16 3 3 Operating Requirements 17 3 4 Physical Characteristics 18 PTMC bezel 19 Part number and serial number 19 K...

Страница 4: ...Memory Map 39 7 2 Serial EEPROM 40 7 3 DS3 Framer and Multiplexer 44 7 4 T8110 Programming 44 7 5 CPLD 48 Serial EEPROM control 48 EBUS control 48 CPLD registers 48 Board ID Register BID 49 Interrupt...

Страница 5: ...rt mapping PORTMAP 2 23 4 2 TEMUX block diagram 25 4 3 Rear I O support 26 6 1 wanPTMC 256T3 TDM data path structure 33 6 2 wanPTMC 256T3 clocking structure 34 6 3 Clock and frame phase relationship 3...

Страница 6: ...errupt sources 36 7 1 wanPTMC 256T3 memory map 39 7 2 Instruction set for 93LC46A 40 7 3 EEPROM byte write example 42 7 4 EEPROM byte read example 43 7 5 T8110 address map as seen from host 45 7 6 T81...

Страница 7: ...ule This manual is intended for hardware and software engineers who are incorporating the wanPTMC 256T3 into a system The wanPTMC 256T3 Technical Reference includes the following Introduction and back...

Страница 8: ...s are numbered starting with 0 Bit 0 is the least significant and bit 7 is the most significant bit of a byte Unless otherwise noted register bits that are identified as unused do not affect the funct...

Страница 9: ...00 Exar XRT7300 E3 DS3 STS 1 Line Interface Unit Data Sheet Rev 1 0 7 Lucent Ambassador T8110 Data Sheet Jan 2001 PICMG 2 3 R1 0 PMC on CompactPCI Specification August 7 1998 PICMG PICMG 2 5 R1 0 Comp...

Страница 10: ...10 About This Manual wanPTMC 256T3 Technical Reference 0 A August 5 2002...

Страница 11: ...tes a fully channelized T3 port with an HDLC SS7 transparent controller and a PTMC interface This product uses the Conexant CN8478 MUlti channel SYnchronous Communications Controller MUSYCC as the PCI...

Страница 12: ...ecautions Caution The adapter should be handled only by trained service personnel at an approved ESD workstation Refer to ANSI IPC A 610 developed by the Institute for Interconnecting and Packaging El...

Страница 13: ...I O panel The gasket around the wanPTMC 256T3 bezel makes a tight fit to ensure an electromagnetic seal Check that the bezel and gasket are pressed firmly into the carrier I O 3 Press the wanPTMC 256T...

Страница 14: ...service you must obtain a Return Material Authorization RMA number from SBE TEL 800 925 2666 Toll free USA TEL 925 355 2000 Outside of USA FAX 925 355 2020 Ship all returns to SBE s USA service cente...

Страница 15: ...tions for the wanPTMC 256T3 communications controller Figure 3 1 is a block diagram of the wanPTMC 256T3 functionality Figure 3 1 wanPTMC 256T3 functional block diagram CT bus rear I O support magneti...

Страница 16: ...tem memory at a rate of 132MBps Logical channels can be mapped as any combination of DS0 time slots to support ISDN hyperchannels Nx64Kbps or as any number of bits in a DS0 for subchanneling applicati...

Страница 17: ...e supported The wanPTMC 256T3 requires both 5V and 3 3V power Caution Bring the wanPTMC 256T3 communications controller to operating temperature in a noncondensing environment The rate of change in bo...

Страница 18: ...ure 3 2 wanPTMC 256T3 physical profile Agere T8110 MUSYCC CN8478A PMC TEMUX Altera Max PMC Pn1 PMC Pn2 PMC Pn3 PMC Pn4 Table 3 1 wanPTMC 256T3 dimensions Depth 5 866 inches Width 2 913 inches Primary...

Страница 19: ...ically accessible serial number is also programmed into non volatile memory during the manufacturing process Keying The wanPTMC 256T3 can be operated in a 5V or 3 3V signaling environment The signalin...

Страница 20: ...ndards Compliance The wanPTMC 256T3 complies with the following industry standard specifications PCI Local Bus Specification Revision 2 1 3 7 Agency Compliance The wanPTMC 256T3 is designed to comply...

Страница 21: ...all HDLC processing and Function 1 access to EBUS configuration cycles Implements universal signaling 3 3 V I O and 5V tolerant by wiring MUSYCC Vgg pin to PCI VIO pin INTA and INTB are supported INTA...

Страница 22: ...hat it is capable of performing PCI protocol see Table 4 1 The wanPTMC 256T3 responds within 10 PCI clock cycles after detecting the state of BUSMODE 4 2 pins Table 4 1 BUSMODE support BUSMODE 4 2 sta...

Страница 23: ...Configuration Register In this mode serial port 0 is logically connected to channel groups 0 1 2 and 3 and serial port 1 is logically connected to channel groups 4 5 6 and 7 See Figure 4 1 Figure 4 1...

Страница 24: ...n the LIU on wanPTMC 256T3 This feature is provided in the TEMUX The LIU provides three interrupts no transmitter output receiver loss of lock receiver loss of signal These interrupts are enabled disa...

Страница 25: ...block diagram See Section 6 1 Data Path Architecture and Section 6 2 Clocking and Data Timing for information on connection of TDM highways and clocks 4 5 T8110 Time Slot Interchange The Agere Systems...

Страница 26: ...the front I O and the rear I O LED signals are tri stated This meets the requirement for isolation of all signals on Pn4 When software selects rear I O mode by setting bit 7 in LTXR register the multi...

Страница 27: ...RSVD PCI RSVD 10 11 Ground 3 3Vaux 12 11 BUSMODE2 3 3V 12 13 CLK Ground 14 13 RST BUSMODE3 14 15 Ground GNT 16 15 3 3V BUSMODE4 16 17 REQ 5V 18 17 PME Ground 18 19 V I O AD 31 20 19 AD 30 AD 29 20 21...

Страница 28: ...e Pin Pin Signal name Signal name Pin 53 AD 06 AD 05 54 53 3 3V PMC RSVD 54 55 AD 04 Ground 56 55 PMC RSVD Ground 56 57 V I O AD 03 58 57 PMC RSVD PMC RSVD 58 59 AD 02 AD 01 60 59 Ground PMC RSVD 60 6...

Страница 29: ...I O pin assignments Pin Signal name Signal name Pin 1 TRING TTIP 2 3 N C N C 4 5 N C N C 6 7 N C N C 8 9 RRING RTIP 10 11 N C N C 12 13 N C N C 14 15 N C N C 16 17 N C N C 18 19 N C N C 20 21 N C N C...

Страница 30: ...2 3 GND N C 4 5 MDC N C 6 7 N C GND 8 9 PTID2 N C 10 11 PTGNDZ1 N C 12 13 REF_CLK GND 14 15 GND N C 16 17 CT_FA N C 18 19 CT_FB GND 20 21 PTID0 N C 22 23 PTGNDZ2 N C 24 25 CT_C8A GND 26 27 GND CT_D19...

Страница 31: ...state of the board This is a useful troubleshooting indicator When the bi color LED CR2 is red it indicates if 2 5V is bad under voltage condition These LEDs are located on the secondary side of the...

Страница 32: ...5 1 MUSYCC registers to set for proper connectivity with T8110 Register Name Register Offset Value Description DUAL_ADR_PTR 0x0004 0x0000 32 bit memory addressing GLOBAL CONFIGURATION DESCRIPTOR 0x060...

Страница 33: ...itecture 33 6 Architecture 6 1 Data Path Architecture Figure 6 1 wanPTMC 256T3 TDM data path structure 7x H MVIP T1 E1 data 7x H MVIP CAS data 1x H MVIP CCS data DS3 data PCI bus CT bus Lucent T8110 C...

Страница 34: ...OUT pin a CTCLK that is synchronized to the recovered clock from TEMUX Figure 6 3 shows the phase relation of various clocks and frames It also shows the width of the frame pulses required in terms of...

Страница 35: ...e the clock rate for the received T1 data may generated by an external source the T8110 must utilize the recovered clock RECVCLK1 RECVCLK2 from the TEMUX and synchronize all TDM highways to it This im...

Страница 36: ...Interrupt Enable Register see Interrupt Enable Register IER on page 49 When INTB is asserted the host reads the Interrupt Source Register in the CPLD to determine which device asserted the interrupt F...

Страница 37: ...TMC 256T3 interrupt structure 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 IPR read write IER read only L_RLOS L_RLOL L_NTO TEMUX DTACK SYSERR CLKERR L_RLOS L_RLOL L_NTO TEMUX DTACK SYSERR CLKERR EBUS_INT Interrup...

Страница 38: ...ta transfer cannot be completed in the fixed EBUS cycle time Even though the T8110 provides the DTACK signal it cannot be used to control the EBUS cycle timing Thus the status of the DTACK signal is l...

Страница 39: ...dresses are for reference they are used only for decoding purposes within the CPLD Only the PCI address is of interest to the host Table 7 1 wanPTMC 256T3 memory map Device PCI address range EBUS addr...

Страница 40: ...serial fashion Table 7 2 shows the instruction set for the 93LC46A device Please refer to the Microchip 93LC46A specification for further details Note that each bit in Table 7 2 represents one PCI wri...

Страница 41: ...ycle Thus during any instruction the host must set AD2 to 1 for every single write In addition to write read of bits specified in Table 7 2 the host must write of 0x00 to the EEPROM at the end of the...

Страница 42: ...Address A5 6 Write 00000101 B 0x05 Address A4 7 Write 00000100 B 0x04 Address A3 8 Write 00000101 B 0x05 Address A2 9 Write 00000100 B 0x04 Address A1 10 Write 00000101 B 0x05 Address A0 11 Write 000...

Страница 43: ...the end of the cycle insures that the minimum time between successive accesses is satisfied Table 7 4 EEPROM byte read example Access type Data value AD 7 0 Phase 1 Write 00000101 B 0x05 Start Bit 2...

Страница 44: ...sheet for more information 7 4 T8110 Programming Under certain situations a read or write to T8110 may take longer than the EBUS cycle This will cause an invalid read or write T8110 provides a DTACK s...

Страница 45: ...ses to complete the operation the DTACK bit should be monitored after the second access so the access to T8110 is not interrupted Table 7 5 T8110 address map as seen from host Region Sub region Range...

Страница 46: ...sient clock errors lower 0x244 Status 3 latched clock errors upper Status 2 latched clock errors lower 0x248 Status 5 Status 4 0x24C Status 7 system error upper Status 6 system error lower 0x250 Reser...

Страница 47: ...6 width 0x8E0 FG7 upper start FG7 lower start 0x8E4 FG7 Rate FG7 width 0x8E8 FG7 counter high byte FG7 counter low byte 0x8EC FG7 mode upper FG7 mode lower 0x900 FGIO read mask FGIO data register 0x90...

Страница 48: ...PLD and only the PCI address is of interest to the host CPLD registers The CPLD implements eight registers that allow configuration of the board Table 7 7 provides the name and description of various...

Страница 49: ...orresponding bit in Interrupt Pending Register will be set if the source generates an interrupt However no interrupt will be generated on PCI INTB See Section 6 3 Interrupts for additional details on...

Страница 50: ...R must be AND ed with the IER prior to use Writing a 1 to bits DTACK L_NTO L_RLOL and L_RLOS clears the pending interrupt An interrupt from CLKERR SYSERR or TEMUX must be cleared in the appropriate de...

Страница 51: ...0C bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Default Value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit Name RIO RSVD RSVD RSVD RSVD TXOFF TAOS LBODIS RIO Enable Rear I O 0 1 Front Pa...

Страница 52: ...0010 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Default Value 0 0 0 0 0 0 0 1 R W R W R W R W R W R W R W R W R W Bit Name RSVD RSVD MLOS LOSTHR RSVD RLB LLB REQEN MLOS Mute on Loss of Signal 0 1...

Страница 53: ...W R W R W R W R W R W Bit Name RATE1 BLNK1 G1 Y1 RATE0 BLNK0 G0 Y0 Table 7 14 LED23 PCI offset address D0018 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Default Value 0 0 0 0 0 0 0 0 R W R W R W R...

Страница 54: ...W R W R W R W R W R W R W R W R Bit Name RST_TMX RST_T8 CCS_EN PTENB RST_TMX Reset TEMUX 0 1 Negate TEMUX Hardware Reset Assert TEMUX Hardware Reset RST_T8 Reset T8110 0 1 Negate T8110 Hardware Reset...

Страница 55: ...t Patch Panel and the remote terminal equipment It is recommend that the Receive Equalizer be enabled by setting the REQEN bit bit 0 in LRXR register The only time the Receive Equalizer should be disa...

Страница 56: ...h between the Transmitting Terminal and the DSX 3 is greater than 225 feet disable the Transmit Line Build Out circuit by setting the LBODIS bit When the Transmit Line Build Out is disabled the LIU ou...

Страница 57: ...of trace is unterminated and appears as capacitor at the end of the line This applies to front I O and rear I O Route the transmit pair as a 75 ohm edge coupled differential pair on the wanPTMC 256T3...

Страница 58: ...receive side is important The 100 ohm line between the transformer on the RTM and the multiplexer on the wanPTMC 256T3 can be made to appear as 75 ohm by carefully adjusting the terminations A 100 ohm...

Страница 59: ...al for coupling in the connectors and on HW400c M based on spacing rules that were specified to ease routing There has been no experimental verification It is possible that the low speed pairs can be...

Страница 60: ...S 9 10 RING2 HS RTIP 11 12 13 14 15 16 N C TIP3 HS 17 18 RING3 HS N C 19 20 21 22 23 24 25 26 LED1 LED_AY LED_AG LED2 27 28 N C TIP4 HS 29 30 RING4 HS N C N C TIP5 LS 31 32 RING5 LS N C 33 34 35 36 LE...

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