wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002
HDLC/SS7 Packet Processor 23
4-2. HDLC/SS7 Packet Processor
The HDLC/SS7 controller is implemented in the Conexant CN8478
MUltichannel SYnchronous Communications Controller (MUSYCC). It can
format and de-format up to 256 logical HDLC channels that can span across
multiple time slots or within sub-rates. The data is then transferred across the
PCI Bus into system memory.
The CN8478 should be configured to operate in PORTMAP=2 mode (bits [1:0]
of the Global Configuration Register). In this mode, serial port 0 is logically
connected to channel groups 0, 1, 2, and 3, and serial port 1 is logically
connected to channel groups 4, 5, 6, and 7. See Figure 4-1.
Figure 4-1 Serial port mapping (PORTMAP=2)
Each port operates at 8.192Mbps (i.e., 4xE1 rate). Frame synchronization
pulses occur at 8KHz and are generated using Frame Group outputs of
T8110. See Section 6-2 for more information on clock timing requirements
and phase relations.
PORTMAP = 2
Channel group processor 3
Channel group processor 7
Channel group processor 0
Serial port 0
Channel group processor 2
Channel group processor 1
Channel group processor 4
Serial port 1
Channel group processor 6
Channel group processor 5
