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HighWire HW400c/2 User Reference Guide Rev 1.0

___________________HighWire

HW400c/2

User Reference Guide

M8275, Rev 1.0

October 10, 2006

Page

Содержание HighWire HW400c/2

Страница 2: ...ut notice SBE Inc and the SBE logo are trademarks of SBE Inc All other trademarks and copyrights are owned by their respective companies About SBE Inc SBE designs and provides IP based networking solu...

Страница 5: ...ions 7 2 8 1 Safety 7 2 8 2 US and Canadian Emissions 7 2 8 3 European Emissions and Immunity 7 2 9 Agency Compliance 7 2 10 Physical Properties 8 2 10 1 HW400c 2 Front Panel 9 2 10 2 Part number and...

Страница 6: ...MV64462 System Controller Ethernet Interface 28 3 4 3 Front Panel RJ 45 Ethernet Interface 28 3 4 4 PT5MC Ethernet Ports 29 3 4 5 CompactPCI Packet Switch Backplane cPSB Ports 29 3 4 5 1 CompactPCI Co...

Страница 7: ...1 Extended Type Register ETR 53 4 2 12 Hardware Revision Register HRR 54 4 2 13 PLL Configuration Register A PLLA 54 4 2 14 PLL Configuration Register B PLLB 55 4 2 15 LED Register B LEDB 56 4 2 16 De...

Страница 8: ...niversal Bootloader 76 5 5 1 1 U boot commands 76 5 5 1 2 U boot environment variables 77 5 5 1 3 Power up call trace 79 5 5 2 Booting with tftp 80 5 5 2 1 U boot parameters for tftp with bootp 80 5 5...

Страница 9: ...12 Front panel Ethernet RJ 45 LEDs 28 Figure 13 IPMI Block Diagram 40 Figure 14 HW400c 2 Network and System environment 67 List of Tables Table 1 HW400c 2 Operating Environment 5 Table 2 HW400c 2 Phy...

Страница 10: ...dress 0x04 48 Table 31 Board Select Register BSR Offset Address 0x05 49 Table 32 LED Register A LEDA Offset Address 0x06 49 Table 33 Memory Option Register MOR Offset Address 0x07 50 Table 34 Geograph...

Страница 11: ...ble 52 Read Byte Count Register RBC Offset Address 0x1D 59 Table 53 Write Byte Count Register WBC Offset Address 0x1E 60 Table 54 SPI Data Registers SDRn Offset Address 0x20 0x27 60 Table 55 SPI Error...

Страница 12: ...ber in preceded by H represents a Hexadecimal value A number in preceded by B represents a Binary value A register or bit name that ends with _EN indicates an enable function A register or bit name th...

Страница 13: ...for those who are installing the HW400c 2 into a system The HighWire HW400c 2 User Reference Manual includes the following Introduction and background on the HighWire HW400c 2 Hardware reference mate...

Страница 14: ...ear I O support 2 1 Product Description The HW400c 2 is built on SBE s advanced HighWire core architecture and features the MPC7447A PowerPC processor Marvell Discovery III system controller up to 1GB...

Страница 15: ...RAM 10 100 1000 Phy Enet MAC Processor Motorola MPC7447A Phy Phy Figure 1 HW400c 2 Block Diagram 2 2 Unpacking Instructions If the carton is damaged when you receive it request that the carrier s agen...

Страница 16: ...to work on the board must be grounded Any person handling the board must be grounded Check alignment and polarization of cables and connectors before applying power Do not apply external voltages to...

Страница 17: ...2 is designed to function within the environment shown in Table 1 Table 1 HW400c 2 Operating Environment Storage temperature 40 to 85 C 40 to 185 F Operating temperature 0 to 55 C 32 to 131 F ambient...

Страница 18: ...ollowing specific parameters were used Prediction method Method I Parts count procedure Application conditions Case 1 1 hr burn in 50 electrical stress Environment Controlled fixed ground mult factor...

Страница 19: ...ied Body CB Report pending 2 8 2 US and Canadian Emissions FCC Part 15 Class B pending Industry Canada CS 003 pending 2 8 3 European Emissions and Immunity EN 50082 1 pending EN 300386 2 supercedes EN...

Страница 20: ...HW400c 2 product Figure 2 shows the physical profile of the HW400c 2 board Table 2 HW400c 2 Physical Dimensions Length 9 2 inches 233 68 mm Width 6 3 inches 160 02 mm Maximum component height front 0...

Страница 21: ...anel has custom cut outs with the appropriate thickness to accommodate two PTMC bezels with EMC gaskets two RJ 45 connectors blue Hot Swap LED green power LED and status LEDs Figure 3 below shows an i...

Страница 22: ...speeds and bus widths see Sections 3 2 3 and 3 2 4 All b All boards are serialized physically with a bar code serial number label and affixe th 2 Keying on the HW400c 2 is used to prevent damage to t...

Страница 23: ...requirements VIO 5 0V 3 3V Current A 5 0V Current A 12V Current A Total Power W HW400c 2 alone 2 26 6 135 0 05 38 73 PTMC site A capacity 4 54 2 8 0 92 40 02 PTMC site B capacity 4 54 2 8 0 92 40 02...

Страница 24: ...ct Configurations The HW400c 2 can be manufactured with several configuration options Specific options include processor type and speed memory amount and CompactPCI connector configuration See Table 6...

Страница 25: ...sor variants available for the board which utilize the Freescale MPC7448 PowerPC Processor with a 200 MHz system bus speed The operating frequency and power consumption for each processor variant is s...

Страница 26: ...6 pin header part of J8 J9 see Figure 2 Figure 5 and Table 7 on the board that accepts the standard SBE developer s debug cable with toggle switch Contact SBE Technical Support for additional details...

Страница 27: ...with TWSI cable for Factory use only 1 O Non Maskable Interrupt NMI The o indicates pin one Used in conjunction with J8 5 holds microprocessor Non Maskable Interrupt NMI active 2 none N C 3 none Rese...

Страница 28: ...or s COP Common On chip Processor port for factory development purpose b Figure 8 COP JTAG Pinout rpose Jumper Block 3 1 5 Special Pu Jumper block J7 located along the top of the board is used for dia...

Страница 29: ...sor memory PCI and evice busses see Figure 1 This section outlines the devices and functions rfaced to the MV64462 3 2 1 System Bu nd Marvell V64462 system controller is a 64 bit bus operating at a sp...

Страница 30: ...pliant node card must have the ability to operate without the presence of the CPCI bus CPCI connectors J1 and J2 are present as they provide power and geographic addressing information however pin B6...

Страница 31: ...to the CompactPCI host processor The local PCI bus is independent of the ho b The local PCI Bus I O voltage is connected to 3 3 volts only Therefore PTMC modules with 5 volt only I O signals cannot be...

Страница 32: ...ss Header Byte 2 0xA0 SBE MAC Address Header Byte 1 0x00 0x06 Board Serial Number BCD Byte 1 0x12 SBE MAC Address Header Byte 3 0xD6 0x07 Board Serial Number BCD Byte 3 0x56 Board Serial Number BCD By...

Страница 33: ...te 0 0xFF 0x2F Netmask byte 3 0x00 Netmask byte 2 0xFF 0x30 Baud byte 1 0x36 Baud byte 0 0x39 0x31 Baud byte 3 0x30 Baud byte 2 0x30 0x32 Baud byte 1 0x30 Baud byte 0 0x00 0x33 CRC32 byte 3 N A CRC32...

Страница 34: ...evice with a 32 bit wide data bus necessary for the processor to boot The device supports burst reads and writes 3 2 7 2 Boot PROM A 4 Mbit 512 KB Boot PROM device is supported in a PLCC socket XU4 th...

Страница 35: ...onfigured as a source of interrupt to either the MPC744X processor or to the CompactPCI host through the PCI interrupt output The IPMI controller can also detect a Watchdog timeout by checking the app...

Страница 36: ...REQ from PTMC Site A MPP4 0x1 PCI1_GNTn 1 Out Low GNT to PTMC Site B MPP5 0x1 PCI1_REQn 1 In Low REQ from PTMC Site B MPP6 0x0 GPIO6 Out Low Disk on Chip Lock MPP7 0x4 INITACT Out High I2C EEPROM Act...

Страница 37: ...0 standard mapping It can access any of the 4096 time slots carried on the H 110 bus The local CT bus with 32 bi directional TDM connections can be programmed for data rates of 2 048Mb s 4 092Mb s or...

Страница 38: ...ck Diagram Control for the local A and B bus drivers is provided by bits 4 5 6 and 7 in the Clock Select Register CSR Refer to Section 4 2 1 for further details Figure 11 shows the implementation Figu...

Страница 39: ...Gigabit MACs with external RGMII connections nments Switch P lt HW400c 2 configuration has the H 110 interface installed However in 2 board is used in a PICMG 2 16 chassis that does not C23 is not gr...

Страница 40: ...reen when the network link is up Hz for 10 Mb s Tx or Rx blinking at 6 Hz for 100 Mb s Tx or Rx gisters Initialization and Monitoring The switch is initialized and its registers polled by utilizing it...

Страница 41: ...ied for Packet Switching Backplane PSB in PICMG 2 16 See Table 14 and Table 15 The HW400c s configure PCIG 16 Node c 3 4 5 1 CompactPCI Connector J3 pow and ground The H 400c 2 us of the J3 designa th...

Страница 42: ...tPCI m which the status of all eight ports can e the CPLD which contains a state ac LED Interface section in the BCM5388 datasheet The HW400c 2 includes eight on board LED Ethernet ports The LEDs are...

Страница 43: ...and D in Figure 3 and by default are not present The left LED indicates Link Activity Speed and the right LED indicates ollision detection for the selected port A port is selected by setting the appr...

Страница 44: ...e lines cannot be used by the PT2MC cards 3 5 3 PMC Type he PMC mezzanine card support includes connection to the local PCI bus 32 bit 33 133 MHz PCI or PCI X and 55 he CompactPCI J5 backp cards have...

Страница 45: ...ts 5 W tts atts 2 4 ts Optional High Powe 4 26 4 Wat 1 W 7 5 W 2 4 Wat r with J ts 6 5 atts atts ts The sta rsion wi er supplied from t pactPCI J4 connect ds the hig t power rat for the mezzanine card...

Страница 46: ...17 REQ 5V 18 17 PME Ground 18 19 V I O AD 31 20 19 AD 30 AD 29 20 21 AD 28 AD 27 22 21 Ground AD 26 22 23 AD 25 Ground 24 23 AD 24 3 3V 24 25 Ground C BE 3 26 25 IDSEL AD 23 26 27 AD 22 AD 21 28 27 3...

Страница 47: ...NDZ LCT D21 24 25 LCT C8A Ground 26 25 LCT C8A Ground 26 27 Ground LCT D19 28 27 Ground LCT D19 28 29 LCT D18 LCT D17 30 29 LCT D18 LCT D17 30 31 LCT D16 Ground 32 31 LCT D16 Ground 32 33 Ground NETRE...

Страница 48: ...Jn4 t pact PCI nect or P MC the sig ls fo thernet p ink Ports and B Lin LPb Link Port B for PTMC Site A go to the Eth itch ports d 4 ectiv 14 MC net k connectio thr must ormer upled or link establish...

Страница 49: ...27 cPCI J5 D17 cPCI J5 C17 28 27 cPCI J5 D17 cPCI J5 C17 28 29 cPCI J5 B17 cPCI J5 A17 30 29 cPCI J5 B17 cPCI J5 A17 30 31 cPCI J5 E16 cPCI J5 D16 32 31 cPCI J5 E16 cPCI J5 D16 32 33 cPCI J5 C16 cPCI...

Страница 50: ...D8 cPCI J5 C8 18 17 Ground Ground 18 19 cPCI J5 B8 cPCI J5 A8 20 19 LPb DB LPb DD 20 21 cPCI J5 E7 cPCI J5 D7 22 21 LPb DB LPb DD 22 23 cPCI J5 C7 cPCI J5 B7 24 23 Ground Ground 24 25 cPCI J5 A7 cPCI...

Страница 51: ...ts from the CompactPCI J2 or J4 connector for reading the physical slot address Figure 13 shows the major functions of the Zircon PM controller Table 22 lists the GPIO port functions sts are installed...

Страница 52: ..._15 GPIO_19 Inputs Geographical Address bits 4 0 GPIO_20 GPIO_23 Inputs Boot Status bits 3 0 3 6 2 Temperatu rt 1 on the Zircon PM The 1 1V MPC744X core oltage 2 5V 3 3V 5V and other supply voltages a...

Страница 53: ...Monitor There are four 4 register bits in the CPLD reserved for indicating the boot status le T ted IO port as shown in Tab power up default va r valu r SBE us Ejector Latch Detection T otherwise know...

Страница 54: ...mmed on MV Serial Interface TWSI See Table 7 The IPMI EEPROMs pre programmed at the factory should always be used Programming on board is usually unnecessary and is recommended only for expert users a...

Страница 55: ...11 and 12 are assigned as he three least significant bits of the Product ID numbers for the HW400c 2 board are always 111 to maintain continuity with the earlier HW400 Product ID ent scheme The LSB v...

Страница 56: ...The Ethernet PSB sig s operation There are power pins assi Section 3 4 5 1 The the Hot Swap controller 3 7 3 Hot Swap on J4 Signals to and from th J ge of 0 7V This voltage is r 3 7 4 Hot Swap on J5 T...

Страница 57: ...een inse li 0 4 stem bo zes the HW4 to turn ff the board E an 5 Th s the PC of the o e D r that the board is functio EXTRACTION is extracted from the en sure the fo ompactPCI ejector is d down to star...

Страница 58: ...56MB Mem0 Mem1 6 MB 0FF FFF SDRAM 25 256 MB 0 F F Mem0 Mem1 2 MB B 1FF FFF SDRAM 512MB 51 512 M 0 F F 0 Mem1 GB 3FF FFF SDRAM 1GB Mem 1 1 GB 0 F F Mem0 Mem1 GB 7FF FFF SDRAM 2GB 2 2 GB E000 0000 F 8GB...

Страница 59: ...D Read Only G E Read Write PR General Purpose Register 0 PSR PCI Status Register 0F Read Only ETR Extended Type Register 10 Read Only HRR Hardware Revision Register 11 Read Only P C u LLA PLL onfig ra...

Страница 60: ...L_N1 SRC and C enable N F CT bus _N2 SRC L EF2 PT_NETREF2 not driven by T8110L 1 Local CT Bu PT_NETREF2 driven by T8110L _N1 SRC L EF1 PT_NETREF1 not driven by T8110L 1 Local CT Bus NETREF1 PT_NETREF...

Страница 61: ...CT No Re ARK No Da Ds turned off TLEDB 0 Status LED B off STLEDA 0 Status LED A off 4 2 3 LED Regis its in ED Register B see Section 4 2 15 are set to 11 the contents of LEDA become ctive and drive th...

Страница 62: ...4 s ide e r bo connectors mirroring the bit that in s onfigur ns e g lane r a non H 110 backplane one or the other connector may not be present For a of th grap MG 2 0 and PICMG 2 5 T g d 08 Bit 7 Bi...

Страница 63: ...PTEN vention is required for PTIDx 2 0 010 or 101 which are the codes for PT2MC and PT5MC respectively When either of these codes is e Control Register PCR Offset Address 0x0A Bit 7 Bit 6 Bit 5 Bit 4...

Страница 64: ...ister that can be used to ion to the IPMI controller The HW400c 2 boot status Table 38 General Purpose Register GPR Offset Address 0x0E Bit 7 Bit 0 0 PTMC Site B PCI Incapable P B 0 PTMC Site A PCI In...

Страница 65: ...10 Local PCI Bus running at 100 MHz us running at 133 MHz 4 2 11 Extended he Extended Type Register ETR is a Read Only register that indicates the type of ster BOR is set to 111 The ETR 2 0 bits are...

Страница 66: ...era ase refer to either the MPC7447A or PC7448 Hard Spe ocuments in the PLL Configuration section for table of all po valu Table 42 PLL Configuration Register A PLLA Offset Address 0x12 Bit 7 Bit 6 Bi...

Страница 67: ...e settings for the System bus and Device bus external PLLs Reading this regis a s the Device bus operating frequency Offset ess 0x1 Reserved SPLL1 ed Reserved DPLL1 DPLL0 Reserved SPLL2 Reserv SPLL 1...

Страница 68: ...cate LAN Status On Board LEDs indicate BCM5388 Ethernet Switch Load Status 0 Status D off 1 Status L D D on S L 000 Status LEDs C and D 001 Status LEDs C and D indicate Port 1 Status Status LEDs C and...

Страница 69: ...ert T8110L RESET default state tate 1 Assert Ethernet Switch PHY RESET minimum 5us 4 2 17 CPU Timer Register CTR he CPU Timer Register is a Read Only register It is used for measuring CPU ce The regis...

Страница 70: ...W W RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR0 WRR 7 0 0x77 Warm reset hed 4 2 19 SPI Page egister SP he SPI Page Register is a Read Write register It is used for selecting the desired age when accessing the BCM...

Страница 71: ...Reserved Reserved Reserved SOR2 SOR1 SOR0 SOR 2 0 000 No by 001 Select 2 byte 010 Select 3rd byte th byte 4 2 22 Read Byt Bit 7 Bit 5 Bit 3 Bit 2 1 Bit 0 te offset Select 1st byte nd 111 Select 8 e Co...

Страница 72: ...values ot be uring an SPI rite operation Similarly read values are not affected by writes They are read om the BCM5388 after an SPI read operation and remain until the next operation r write only SDR...

Страница 73: ...ess 0x1F Reser BSY ved Reserved Reserved Reserved BYTER RACKER SPIFER S SB SPI Interface ready for re e ope SPI Interface busy oper rogr PI R 0 SPIF Check passed 1 SPIF Check failed no operation perfo...

Страница 74: ...57 EEPROM Operation Status Register EOSR Offset Address 0x2 Bit 6 Bit 4 Bit WERR d Reserved ERD EWDS R EWEN Reserve EBSY EW R R R R W W W W EWEN Writing a 1 to this bit initiates a EWEN cycle required...

Страница 75: ...Registers EDRn Offset Address 0x2A 0x2B eg ster Offset Byte EDR0 0x2A LSB EDR1 0x2B MSB 4 3 Accessing the Serial EEPROM with 4 3 1 Reading a Register EAR see Section 4 2 25 to the desired word data is...

Страница 76: ...in the EEPROM Oper Section 4 2 26 If set to 0 proceed to the next ste C Check the EBSY flag If set to 0 EWEN is complete proceed to the next step D E Write data bytes to takes 3 ms to complete Check t...

Страница 77: ...count of bytes to read This step initiates reading from the switch to the CPLD An incorrect read value will result if this count exceeds the size of the Ethernet switch register There are no error fl...

Страница 78: ...on 4 2 23 to the count of bytes to write This step initiates writing to the Ethernet switch The register will not be written if this count differs from the size of the Ethernet switch register There a...

Страница 79: ...o summarize the Linux kernel for the HW400c 2 is installed on a host system that also runs Linux See Figur the host system in the opt gentoo directory and must be made available HW400c 2 board via NFS...

Страница 80: ...oard cannot communicate with the system on which you installed the Gentoo Linux distribution make sure that you have either disabled any default firewall installation or that you have at least enabled...

Страница 81: ...to boot your target embedded system over the network using the exported file system as the target s root file system Although you might eventuall ant to use a small specific root file system as an ini...

Страница 82: ...preceded with a hash mark in the file to activate them use your favorite ad U ifying files in the N A You should separately start and stop the NFS service rather than simply restarting it because the...

Страница 83: ...st Linux systems typically use one of two mechanisms to activate and manage network servers such as TFTP servers These are the Extended Internet Services Daemon xinetd t and the older Internet Service...

Страница 84: ...t a running command whose nam separated field in this output is its process ID 578 in this example which is the information that you will need to restart the process After collecting this information...

Страница 85: ...xinetd d The file for the TFTP server is aptly named tftp and looks like the following default off rot col The tftp protocol is often used to boot diskless ork tations download configuration files to...

Страница 86: ...address found in the bootptab file A b tp g bootp daemon bootpd and a bo p nning on your system enter s eaf grep bootpd root 15278 25183 0 2005 pts 1 00 00 18 bootpd d 4 s root 20587 20484 0 15 27 pts...

Страница 87: ...ab ault ds 10 0 0 200 hn johnboy ht 1 ha 00a0d6123456 ip 10 0 100 2 ef bf uImage gw 10 0 0 120 borgus ht 1 ha 000012342222 ip 10 0 100 3 ef bf uImage gw 10 0 0 120 neumann ht 1 ha 000012343333 ip 10 0...

Страница 88: ...the boot environment All commands are available at the debug B help List all commands and environment variables printenv Print a list of all valid environment variables that are currently in use This...

Страница 89: ...bootdelay The delay time in seconds until autoboot executes bootcmd begins A countdown is displayed on the command line Any U boot has large number of environment va t of basic boot variables bootarg...

Страница 90: ...clarification When using bootp the mask is ignored Fixed environment variables These variables will be displayed and cannot be changed ard serial Destination of the HW400c 2 s standard output termina...

Страница 91: ...all to gigateak_setup_arch is made via the function pointer ppc tion pointer is initialized in platform_init 4 gi tra file needed for Gentoo to boot on the HW400c 2 jumps to _start _start arch ppc ker...

Страница 92: ...add d confusion and show that they are not in use d 9600n8 ip bootp nfsroot opt gentoo ot dev nfs rw rverip 0 0 0 0 tewayip 0 0 0 0 tmask 255 255 255 0 din serial dout serial stderr serial Tftp boot...

Страница 93: ...dress and S strings must then ad use the save command to store the variables in non debug print bootargs console ttyMM0 9600 nfsroot o bootfile uImage bootcmd tftpboot bootm bootdelay 5 baudrat ethadd...

Страница 94: ...t gentoo root dev nfs rw PID hash table entries 2048 order 11 32768 bytes time_init decrementer frequency 41 666666 MHz Console colour dummy device 80x25 Dentry cache hash table entries 65536 order 6...

Страница 95: ...ok Loading key mappings ok Setting terminal encoding to UTF 8 ok net eth0 cannot start until the runlevel boot has completed Starting lo Bringing up lo ok NIT Entering runlevel 3 Keeping current conf...

Страница 96: ...level formatting of the disk on chip and to create two binary C wr0 A script that invokes docshell to write uImage kernel wr1 Ramdisk to binary partition 1 E uImage The kernel image The ramdisk image...

Страница 97: ...z saveenv oot variables to NVRAM Then boot from disk on chip as follows docload bootm 400000 800000 Alternately rese uRamdisk has the same intent as a ramdisk on other linux platforms It brings up nec...

Страница 98: ...ely on the HW400c 2 cd usr src linux 2 6 9 gigateak 2 Set the date see man date MMDDHHmmYYYY Where MM 2 digit month YYYY 4 digit year 3 Clean up old config files 5 Create the changes in the config fil...

Страница 99: ...th F www gentoo org There are several HOW TO s for various applications and services located at http gentoo wiki com Index HOWTO 5 6 1 1 Emerge ively on the n automatically a has Emerge can also upda...

Страница 100: ...on the HW400c 2 console etc init d vsftpd start If you want to add xinetd as a default daemon on every start up te login with ssh Gentoo Linux installs sshd by default but it is not enabled Before st...

Страница 101: ...arameters in S b chown_uploads NO ner_file etc v tpd vsft a as _uploa NO _download_enabl round YES n YES ation on ftp can be found at http entoo wiki com HOWTO_vsftpd 5 7 Linux Device Drivers up vice...

Страница 102: ...l IPM 8 Manufacturer ID LSB 0x1F Zircon default is 0 SBE IANA number LSB IANA number 9 Manufacturer ID IANA number 0x04 Zircon 0 SBE IANA number MSB default is 10 Manufacturer ID IANA number 0x00 Zirc...

Страница 103: ...go start application at address addr help print online help icache enable or disable instruction cache icrc32 checksum calculation iloop infinite loop on address range imd i2c memory display iminfo p...

Страница 104: ...send ICMP ECHO_REQUEST to network host printenv print environment variables protect enable or disable FLASH write protection rarpboot boot image via network using RARP TFTP protocol reset Perform RESE...

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