Hardware Manual PCD1.M0160E0 │ Document 27-622
|
Version ENG04 │ 2018-08-20
Saia-Burgess Controls AG
Introduction
Orientation
2-4
2
2.1.3
IO Addressing
Optical output position for the following description
The PCD is lying or hanging in front of us as shown, so that the labelling can
be read from left to right.
Addressing
Integral I/Os on the CPU board of the PLC are assigned to terminal blocks X0 to
X2 and located on the underside of the PLC. They are addressed from right to left,
starting at I/O address 32.
X3
X2
X1
X0
X3
X2
X1
X0
with cover
without cover
All element addresses in the PCD family start from 0
Addressing the inputs or outputs via Saia PG5
®
The CPU’s on-board inputs and outputs can be assigned to flags and registers
(media mapping) by the programmer using the Device Configurator (Device Con
-
figurator in the Saia PG5
®
tool). If IOs are media-mapped, these IOs cannot be
reached directly from the program.
Further details about the programming can be found, among other places, in the
auxiliary system of the Saia PG5
®
programming tool or in the corresponding manu-
als.
Watchdog relay address “O 255”
The address O 255 is reserved for the watchdog relay. The closing relay contact
connection is located at connector X3.
You can find additional details in Chapter 3.8 Hardware watchdog. Please read
this information.